應用於LTE發射機之高增益混頻器與低電壓返馳式轉換器設計

Design of High-Gain Mixer and Low-Voltage Flyback Converter for LTE Transmitter

林正偉(Cheng-Wei Lin)

指導教授 ： 黃育賢 ； 陳建中

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2011年)

摘要

本論文第一部分為使用線性增強技術之高增益雙平衡式混頻器的電路設計。為因應高頻電路應用於積體化電路的特性，混頻器積體化將是一研究重點，不僅降低功率消耗、成本及面積，並可提高混頻器之附加價值。其使用雙平衡式電路架構來提升混頻器線性度及轉換增益，且具有較好的埠對埠隔絕能力，可避免本地振盪器饋通、直流偏移與自我混頻。並於混頻器電路架構上使用線性增強技術，使電晶體操作於線性區，進而改善混頻器之線性度。本電路使用台灣積體電路公司零點一八微米一層多晶矽六層金屬互補式金屬氧化物半導體製程來實現，晶片面積為0.87 x 1.146 mm2 (包含PADs)。
本論文第二部份為使用平均電流控制技術之低電壓返馳式轉換器的電路設計。使用平均電流控制電路取代傳統斜率補償的新型返馳式電路，不僅具有快速暫態響應，且電路複雜度低，能有效提高整體效率及降低成本等優點。控制方式為改良過後的返馳式電源轉換器，將二次側的二極體改為功率電晶體，具有同步整流輸出功能。在低輸出電壓、高輸出電流的情況下，利用其導通後的低電阻特性，能有效地降低順向壓降和功率損耗。本電路使用台灣積體電路公司零點三五微米二層多晶矽四層金屬互補式金屬氧化物半導體製程來實現，晶片面積為2.46 x 2.1 mm2 (包含PADs)。

關鍵字

線性增強技術 ； 雙平衡式混頻器 ； 平均電流控制技術 ； 返馳式轉換器

並列摘要

The first part of this thesis presents a high-gain double-balanced mixer using linearity enhancement techniques. The mixer is an important issue for high-frequency integrated circuit. The proposed mixer not only decreases power consumption, cost and chip area, but also increases extra value of mixer. The double-balanced technique not only improves linearity and conversion gain of mixer, but also has better port-to-port isolated ability which can avoid local oscillator feed through, dc offset and self-mixing. Besides, linearity enhancement techniques are adopted to improve mixer linearity. The proposed circuit has been fabricated with TSMC 0.18μm CMOS 1P6M processes, the total chip area is 0.87 x 1.146 mm2 (include PADs). The supply voltage is 1.8V, and the operating frequency is 2GHz and conversion gain is 16.212dB.
The second part which is a low-voltage flyback converter using average- current-controlled techniques is present in this thesis. The average-current-controlled technique is used to achieve fast transient response and higher efficiency, and the controlled circuitwhich is simple can reduce cost. The proposed flyback converter uses synchronoustopology, instead of the conventional topology, the synchronous flyback converter replaces the secondary side output diode with a power NMOS which causes lower power consumption. The proposed circuit has been fabricated with TSMC 0.35μm CMOS 2P4M processes, the total chip area is 2.46 x 2.1mm2 (include PADs). The supply voltage is 1.5V, and the regulated output voltage ranges is from 1V-3V and switching frequency is 1MHz.

並列關鍵字

linearity enhancement techniques ； double-balanced mixers ； average-current-controlled techniques ； flyback converter

參考文獻

[43] 張晏鐘，加速型脈寬調變與平均電流模式技術之直流-直流降壓轉換器設計，國立臺北科技大學，電腦與通訊研究所，碩士論文，臺北，2010。

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