基於SOPC平台之JPEG-LS影像編解碼系統設計

The Implementation of a JPEG-LS Codec System based on the SOPC Platform

林世偉(Shih-Wei Lin)

指導教授 ： 高立人

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2012年)

摘要

JPEG-LS是非失真以及近乎非失真影像壓縮的國際標準。本論文主要針對非失真模式提出一高效能之JPEG-LS編解碼電路並以軟硬體協同技術將其實現於FPGA。其中編碼器是以管線之架構來設計，而解碼器則是利用軟硬體協同運算的方式設計。為了驗證所設計之編解碼器，我們將編碼器與解碼器分別實現於ALTERA之FPGA 中。所規劃之編碼器電路時脈可以達到113.03MHz，瞬間產出量也可達到113.03MPixel/s，解碼器電路時脈則可以達到105.21MHz。為了驗證本電路之可用性，本論文也實際設計了一套完整的雲端影像編解碼系統，使用者僅需利用可上網之設備，即可透過網頁取得非失真編解碼與儲存之服務。經由各項實驗證明，本研究所提出的電路架構不論在瞬間產出量、使用面積與記憶體使用量等方面均有不錯的表現。

關鍵字

JPEG-LS ； FPGA ； 軟硬體協同設計 ； 管線處理

並列摘要

JPEG-LS is a coding standard for lossless and near-lossless image compression formulated by ITU/ISO. In this thesis, a high performance codec system is proposed and implemented in FPGA for the regular mode in the lossless scheme of JPEG-LS. The encoder is designed by using a pipeline architecture, while the decoder is based on hardware and software codesign. In order to verify the correctness and performance of the proposed codec, the encoder and decoder are implemented in the ALTERA FPGA respectively. The frequency of the proposed encoder circuit can have a clock rate up to 113.03MHz, and the throughput can be up to 113.03MPixel/s. The frequency of the proposed decoder can be up to 105.21MHz. In addition to the proposed codec circuits, we also implement a cloud-based image codec system in this thesis so that the usefulness of the proposed architecture can be demonstrated. In the proposed cloud-based codec system, only a browser is needed for accessing the service of image coding and decoding on the Internet. As we can see in the experiment, the proposed architecture can have a very good performance in terms of throughput, chip area, memory usage, and outperforms existing state-of-the-art JPEG-LS codecs.

並列關鍵字

JPEG-LS ； FPGA ； Hardware and software codesign ； Pipeline processing

參考文獻

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