考慮面積平衡與溫度分佈之層級分割

Multi-Layer Partitioning with Consideration of Area Balance and Thermal Distribution

賴品丞(Pin-Cheng Lai)

指導教授 ： 方志鵬

共同指導教授 ： 張陽郎

國立臺北科技大學/電資學院/電機工程系研究所/碩士(2014年)

摘要

現今積體電路愈來愈龐大且功能越來越複雜，隨著元件愈多密度愈大，複雜電路之元件彼此繞線距離相對變遠，造成連線延遲增加且易繞線失敗，三維積體電路成為一種新的替代方案，其中又以矽穿孔技術(Through-Silicon Vias, TSVs)最為廣泛使用於不同層之垂直通道連接。
在目前三維積體電路設計中，散熱是一項重要的議題。本論文在分層後進一步用面積、TSV個數及功率消耗為成本函數，以模擬退火法調整，使中間層功率密度較低，讓電路更容易散熱。
實驗結果顯示以所提出的方法能達到分層後的功率密度要求，且有效達到各層面積平衡，並減少TSV數量。

關鍵字

三維積體電路 ； 功率密度 ； 分割 ； 面積平衡 ； 平面規劃

並列摘要

Nowadays integrated circuits are getting larger and with more complex functions. As the density of components increases, the routing between components becomes relatively distant, which may raise time latency and cause routing fails. Three-dimensional integrated circuit are viewed as a new alternative solution to such a problem, and through-silicon vias are widely used to connect the different layers.
In the current design of three-dimensional integrated circuits, heat is an important issue, this paper introduce a simulated-annealing based method, which is applied after layer assignment, to further minimize the amount of TSV while considering area balance and power.
Experimental results show that, with our method, the intermediate layers can have acceptable power density, while the area balance is achieved and the amount of TSVs is minimized.

並列關鍵字

3D-VLSI ； Power Density ； Layer Assignment ； Area balance ； Floorplanning

參考文獻

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