iLap: 三維積體電路上減少直通矽穿孔數目之迭代式層級感知分割演算法

相較於二維積體電路，三維積體電路在垂直方向的整合在二維製程技術逐漸面臨瓶頸的情況下提供了進一步提升效能的可能性。此整合技術允許將晶粒做多層堆疊，利用直通矽穿孔(Through-silicon vias, TSVs)進行垂直方向的信號連線。雖然直通矽穿孔被視可行的垂直連線方式，但也伴隨著所佔面積太大及製造過程的良率和穩定度的問題，因此直通矽穿孔的數量在設計電路的過程中是很重要的關鍵。在這篇論文裡，為了最小化直通矽穿孔的數量，我們提出兩種迭代式三維層級感知分割演算法(iLap-2和iLap-k)。iLap-2重覆性地運用二路最小切割演算法，將給定的設計電路從底層往上一層一層地擺放；同時也在不違反輸入及輸出腳位必須在晶片底層的限制下，進而改善三維的積體電路。iLap-k則是基於iLap-2的演算法架構，將iLap-2的二路分割演算法核心用多路分割演算法取代之，使其更能考慮全域的分佈狀況，而達到更好的效果。與其它已習知的方法比較，實驗結果顯示iLap系列的作法在直通矽穿孔的總量和分佈上有相當大程度的改善。以iLap-k為例，相較於以hMetis分割法能達到的最少直通矽穿孔數目，iLap-k能夠達到33%的改善；並且在直通矽穿孔的分佈上，iLap-k顯得更加平均而不會集中在某一層。這項優點不管是針對特定用途而設計的特殊應用積體電路(ASIC)或是規則型架構的電路來說，都可以減少面積以及資源上的損失。

關鍵字

直通矽穿孔；分割；三維積體電路

並列摘要

As compared with two-dimensional (2D) ICs, three-dimensional (3D) integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a good solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, to minimize the number of TSVs becomes important in the design processes. Therefore, in this thesis, we propose two iterative layer-aware 3D partitioning algorithms, named iLap-2 and iLap-k, for TSV minimization. iLap-2 iteratively applies 2-way min-cut partitioning to gradually divide a given design layer by layer in the bottom-up fashion. Meanwhile, iLap-2 also properly fulfills a special I/O pad constraint incurred by 3D ICs to further improve its outcome. Based on iLap-2, iLap-k replaces the 2-way partitioning by k-way partitioning engine for considering the distribution of the future. The experimental results show that iLap-k can reduce the number of TSVs by about 33% as compared to several existing methods. Besides, iLap-k distributes TSVs more evenly among different vertical layers, preventing any layer junction from having a burst number of TSVs. That is important to application specific integrated circuit (ASIC) as well as regular structures.

並列關鍵字

Through slilicon via ； partitioning ； 3D IC

參考文獻

[1] International Technology Roadmap for Semiconductor. Semiconductor Industry Association, 2005 – 2009.

[5] K. L. Tai, “System-in-package (SIP): challenges and opportunities,” Proc. of Asia and South Pacific Design Automation Conference, pp. 191 – 196, 2000.

[7] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: a novel chip design for improving deep submicron interconnect performance and systems-on-chip integration,” Proc. IEEE, vol. 89, pp. 602 – 633, 2001.

[11] I. Loi et al. “A low-overhead fault tolerance scheme for TSV-based 3D network on chip links,” Proc. International Conference on Computer-Aided Design, pp. 598 – 602, 2008.

[14] E. Beyne et al. “Through-silicon via and die stacking technologies for microsystems-integration,” Proc. IEEE International Electron Devices Meeting, 2008.

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iLap: 三維積體電路上減少直通矽穿孔數目之迭代式層級感知分割演算法

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