0.13微米製程N型電晶體在升溫下之熱載子可靠度

DC Hot Carrier Reliability at Elevated Temperatures for nMOSFETs Using 0.13μm Technology

周澤瑋(Ze-Wei Jhou)

指導教授 ： 黃恆盛

國立臺北科技大學/機電學院/機電整合研究所/碩士(2005年)

摘要

一般而言，在電晶體溫度升高，會影響到載子的移動，減少基板電流與熱載子所造成的衰減。然而，有研究指出，高溫下電晶體飽和電流的衰減會因為飽和速度長度的減少，而造成比室溫來得嚴重，但電晶體線性電流仍是低溫比較嚴重。其他的研究指出，熱載子的效應存在著轉位點(電壓)，我們把電晶體閘極偏壓在基板電流的最大值，汲極偏壓在轉位點的上下，會造成基板電流與溫度效應之間的關係反轉。而這個現象形成了0.13微米製程下，熱載子可靠度的一個新的問題。
在本研究論文中，我們採用0.13微米製程技術，通道長度分別為90奈米與120奈米、氧化層閘極厚度為20 Å與32Å、寬度為10微米的n型電晶體，做(1) 25 ℃ (2) 75 ℃ (3) 125 ℃，偏壓設為基極電流最大值的熱載子可靠度試驗，測試元件參數衰減情形。研究發現汲極電流的衰減與基極電流並不一定成必然的關係。外部電晶體元件部份，就算將偏壓設定在低於轉位電壓，觀察汲極電流的衰減，發現並沒有溫度效應反轉的關係存在。而飽和速度效應也並非影響Id,sat衰減的主因之一。比較幾種汲極電流的衰減程度，我們首次發現，對類比電路而言，Id,op是衰減最嚴重的參數，這點非常值得提供類比電路工程師在可靠度設計上作為考量。
另本論文有找出一些熱載子效應的複雜現象，即一般公認基板電流可以反應出熱載子現象是需要再研究的，本論文研究顯示汲極電流的衰減跟基板電流在不同的溫度下趨勢有所不同，理由可能是部份的電洞流到閘極氧化層，穿過飽和速度區域。由於有研究指出電子電洞的結合是形成熱載子衰減的主因，而本研究也指出基板電流已經無法完全反應整個熱載子撞擊的事實。然而想要解決所有的問題，首先要找出飽和速度長度受到溫度與汲極電壓之間的影響，這有待下一步更深入的研究。

關鍵字

數位 ； 類比 ； 熱載子 ； 可靠度 ； 溫度

並列摘要

Attributed to the increasing scattering during the carriers’ moving, substrate current Ib and hot carrier degradation of MOSFETs are prevalently believed smaller at elevated temperature. However, the degradation of saturation drain current Id,sat at high temperature was reported worse due to the reduction of velocity saturation length, but the degradation of linear drain current Id,lin was still smaller with increasing stress temperature. Other related studies showed that the hot carrier effect existed a transition point (voltage), which reversed the dependence of MOSFETs’ Ib to temperature. This finding was proved with the peak substrate current would reverse its temperature dependence when biased drain voltage Vd across the transition point. These seems consistent findings now facing new challenges as we examine the results of DC hot carrier stress on the nMOSFETs of 0.13 µm technology.
In this study, the tested devices were from 0.13 µm technology. The nMOSFETs used in this experiments have Leff = 90 nm with gate oxide thickness of 20Å (Core devices) and Leff = 120 nm with gate oxide thickness of 32Å (I/O devices), all the W = 10 µm. Stress conditions were (1) 25 ℃ (2) 75 ℃ (3) 125 ℃, all at peak substrate current. It is found that the drain currents degradation are not necessary dependent to the Isub. The degradation of the drain currents of I/O devices are found no reverse temperature effect even the stress bias lower than transition point. And the velocity saturation effect may not the main fact to impact the degradation of Id,sat. Comparison with all the drain currents, it is found first time, Id,op is the worst case for designing analog circuits with satisfactory reliability.
Although further studies spanning other nodes of technologies and sizes are required, the study at least shows complicated natural of hot carrier effects. Another significant fact revealed here is the substrate current Ib commonly accepted as the statues for monitoring the drain avalanche hot carrier (DAHC) effect is need to be modified since Id degradation and Ib variations versus temperature have different trends. The reason for this may be parts of holes flow to gate oxide through the velocity saturation region as suggested that the combinations of holes and electrons are the main mechanism of DAHC degradation. Therefore the Ib formulation considered all holes of impact ionization flow to substrate may be not reflecting all the facts. However if this problem is intended to be completely solved, the first question needed to fact is how the velocity saturation length is affected by temperature combining drain voltage variations.

並列關鍵字

Digital ； Analog ； Hot Carrier ； HCI ； Reliability ； Temperature

參考文獻

[1]H. Hwang, J. S. Goo, H. Kwon and H. Shin “Enhandced degradation of nMOSFET’s under Hot Carrier Stress at Elevated Temperatures Due to the Length of Velocity Saturation Region”, 1994 IRW Final Paper.

[2]P. Aminzadeh, M. Alavi, D. Scharfetter “Temperature Dependence of Substrate Current and Hot Carrier-Induced Degradation at Low Drain Bias” 1998 Symposium on VLSI Technology Digest of Technical Papers.

[4] H. S. Huang et al, “A modified C-V method used for Leff extraction and process monitoring in advanced 0.15 m CMOS technology and beyond,” Jpn J. Appl. Phys., vol. 40, 3A, 2001.

[5]T. Ohguro et al, “An epitaxial channel MOSFET for improving flicker noise under low supply voltage,” IEEE VLSI Tech. Digest, pp. 160-161, 2000.

[6] J. H. Huang, Z. H. Liu, “A Physical Model for NMOSFET Output Resistance” , in IEEE, pp.569-572 1992.