90 nm節點窄寬度nMOSFETs於升溫下之HC與PBTI可靠度探討

HC and PBTI Reliability on Narrow Width 90 nm Node nMOSFETs at Elevated Temperatures

江志豪(Chih-Hao Chiang)

指導教授 ： 黃恆盛 ； 陳雙源

國立臺北科技大學/機電學院/機電整合研究所/碩士(2008年)

摘要

在現今CMOS技術中，淺溝槽絕緣(STI)不可避免地使用於相鄰電晶體間的絕緣，但其對熱載子(HC)與正偏壓溫度不穩定性(PBTI)等可靠度的影響，至今仍非常不確定，特別是窄寬度的nMOSFET。
在本研究中，採用聯華電子公司所提供之90 nm節點晶片，且以閘極氧化層厚度為31Å與68Å之nMOSFET為目標。對通道長度/寬度(W/L)=10/0.2與0.22/0.2 um的元件，進行通道熱載子(CHC)與汲極雪崩熱載子(DAHC)加壓測試；對W/L=10/10 um與W/L=0.4/10 um的元件，進行PBTI加壓測試。所有測試皆分別以25℃、75℃與125℃三個溫度進行。在加壓測試後，以閘二極體量測法(gated diode method)分析元件電性。由CHC與DAHC的實驗結果得知，與寬通道元件比較，窄通道nMOSFET所產生之介面狀態(interface state)較多，而使其電晶體性能加速退化。推論於CHC加壓測試後，介面狀態主要在STI邊緣與通道區域產生，而造成嚴重地臨界電壓漂移與汲極電流退化。然而，DAHC加壓測試後，推測只於STI邊緣處產生介面狀態。此外，由PBTI實驗結果得知，隨著溫度與電場的增加，寬通道元件參數漂移略大於窄通道元件，此與HC的情況恰好相反，推測主要原因是當電子因垂直電場注入氧化層時，除規矩分佈外，與HC相較，其有較多比例之陷入電荷分佈於STI的側緣，故窄通道元件之PBTI劣化略小於寬通道。

關鍵字

窄寬度 ； 熱載子 ； 正偏壓溫度不穩定性 ； 閘二極體量測 ； 介面狀態 ； 可靠度 ； 溫度

並列摘要

Shallow trench isolation (STI) is inevitable to be used in isolating the neighboring transistors in today CMOS technology, but their influences on hot-carrier (HC) and positive bias temperature instability (PBTI) reliability is not clear especially on the narrow width nMOSFETs.
In this work, nMOSFETs on wafers from 90 nm node of UMC (United Microelectronics Corporation) were characterized, and those with 31Å and 68Å gate oxide thickness were targeted. The devices with channel width/length (W/L) equal to 10/0.2 um and 0.22/0.2 um were stressed under channel hot carrier (CHC) and drain avalanche hot carrier (DAHC) conditions. Other devices with W/L equal to 10/10 um and 0.4/10 um were stressed under PBTI conditions. All tests were conducted at temperatures of 25, 75 and 125 ℃. After stresses, gated diode method was used to analyze electrical characteristics of these devices. The CHC and DAHC test results show that the degradation of the narrow width nMOSFETs was enhanced by the generations of interface states. We infer that CHC stresses produce interface states both on STI edges and channel region, causing threshold voltage shifts and drain current degradation seriously. However, we infer that DAHC stresses have only produced interface states on STI edges. In addition, from the experimental results of PBTI, the parameter shifts in wide width devices were slightly larger than narrow width devices as the temperature and electric field increased. The results were opposite to HC stresses. The main presumable reason is, when electrons were injected into the oxide by vertical electric field, the trapped electrons were uniformly located in the channel region and STI sidewalls. This distribution can be attributed to the reason explaining why, contradictory to HC, PBTI has caused the degradation of narrow width devices slightly small than wide width devices.

並列關鍵字

Narrow Width ； Hot Carrier ； PBTI ； Gated Diode Measurement ； Interface State ； Reliability ； Temperature

參考文獻

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