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  • 學位論文

90 nm 節點MOSFETs之熱載子及偏壓溫度不穩定性效應

Hot-Carrier and Bias Temperature Instability Effects on 90 nm Node MOSFETs

指導教授 : 黃恆盛 陳雙源
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摘要


熱載子(hot carrier, HC)效應是個主要的可靠度問題,在早期的研究中,金氧半場效電晶體(MOSFET)的HC最劣化情況是在室溫時之汲極雪崩熱載子(DAHC)模式,然而近幾年的研究指出最劣化情況已從DAHC改變到通道熱載子(CHC)模式,且溫度方面已從低溫變化到高溫。另外,近年來隨著閘極氧化層厚度的緊縮,負偏壓溫度不穩定性(NBTI)影響正通道MOSFETs劣化的問題,變的更加嚴重,因此理解這些可靠度問題的嚴重程度是非常重要的。 本研究採用聯華電子公司(UMC)所提供之90奈米製程晶片,實驗分為兩部分,第一部份探討在不同氧化層厚度下,pMOSFET的NBTI效應;第二部份探討n及pMOSFET的HC及BTI效應,研究測試元件的最劣化條件。 藉由I-V及閘極二極體(gated-diode)的量測,第一部份的實驗發現,對具31 Å SiON介電層,在25℃時,氧化層陷入電荷( oxide trapped charges, Not)為主要NBTI之劣化機制,而高溫時,劣化機制轉變成以產生介面狀態電荷(interface-state charges, Nit) 為主;而對具68 Å SiON介電層之pMOSFET言,室溫時,由Not主導NBTI劣化機制,但在高溫時卻是由Nit和Not主導。推測對16 Å SiON之pMOSFET,其劣化機制應與31 Å SiON之pMOSFET相同。有關第二部份最劣化條件的問題,經由多次實驗,對奈米級n及pMOSFET的加壓測試,最劣化條件為在高溫下的CHC模式。對pMOSFETs言,實驗也顯示NBTI的劣化較DAHC來的嚴重,由壽命公式推估,對較薄介電層之電晶體,其NBTI所造成pMOSFET的劣化也愈來愈嚴重。

並列摘要


Hot carrier (HC) effect is a critical reliability problem. In early researches, HC of MOSFET showed the worst degradation at DAHC mode low temperature. However, a recent study reported that the worst case has switched from DAHC to CHC mode from low to high temperature. Furthermore, In recent years, NBTI induced pMOSFET’s degradation has become more serious as oxide thickness keeps thinning. Therefore, it is important to under the degrees of severity of there reliability issues. In this research, from 90 nm node wafers from United Micro-electronics Corporation (UMC) were used to explore these reliability issues. Two types of experiments were conducted in this work. The first one is to investigate the NBTI effects of pMOSFETs using different oxide thicknesses. The other one is to determine n- and pMOSFETs the worst case between HC and BTI effect. By I-V and gated diode measurements, the experiments of the first part reveal, that for 31 Å SiON dielectric at 25℃, oxide trapped charges (Not) dominate the NBTI degradation mechanism. However, at high temperature, the NBTI degradation mechanism switches to the generation of interface-state charges (Nit). For 68 Å SiON dielectric, the Not also dominate the NBTI degradation mechanism at room temperature, but Nit and Not determinate the NBTI degradation mechanism at high temperature. It is measurable that pMOSFETs of 16 Å SiON dielectric, also possess similar degradation mechanism as 31 Å SiON dielectric. In the part two of the worst case question, through many experiments of stressing, the nano n- and pMOSFETs, the worst case is found to be CHC mode at high temperature. For pMOSFETs, the NBTI stress exhibits more degradation than DAHC stress. Estimated by the lifetime formula, NBTI induced pMOSFETs degradation will become more serious as more and more thinner dielectric is used.

參考文獻


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