低電源雜訊之電流模式低壓降穩壓器

Low Power-Bounce Current-Mode Low Dropout Voltage Regulator

潘財明(Chan-Min Pan)

指導教授 ： 陳建中

國立臺北科技大學/電資學院/電子電腦與通訊產業研發碩士專班/碩士(2007年)

https://doi.org/10.6841/NTUT.2007.00277

摘要

電流模式低壓降穩壓器的電路架構包括放大器電路、疊接式電流鏡、緩衝器、電流回授電路所組成。低壓降穩壓電路是將輸入的訊號降至所需的電壓訊號且能穩定輸出。因為放大器的增益很大讓輸出訊號誤差很小，所以可以讓輸出電壓訊號正常穩定在額定電壓。最大的效果是可以消除電源雜訊以及接地雜訊，一般電路在電源端及接地端會有電感效應，所以電流模式可以減少電流流過電感元件所產生的電感效應，且加入的緩衝器電路可以使負載調節率變好，恢復時間也就變快。

本論文電路是使用台積電點三五微米互補式金氧半製程來實現，而工作電壓範圍在3V，電流模式低壓降穩壓器輸入電流訊號範圍185mA~350mA，輸出電壓穩在1.8V，最大效率為97.3%，此晶片包括1177顆電晶體，晶片面積0.783×0.875mm2。

關鍵字

低壓雜訊之電流模式 ； 電源雜訊 ； 接地雜訊 ； 暫態電流

並列摘要

The current-mode LDO contains error amplifier, buffer stage and current feedback. The LDO circuit can produce a stable output voltage and the output voltage is smaller than input voltage. The open-loop gain of error amplifier is about 80 db, which allows the output voltage of error amplifier to be very accurate. The current-mode LDO can reduce power-bounce and ground bounce, which allows the improvement of inductance effect on the power and ground line. Adding the buffer stage and current feedback circuit between error amplifier and the output of the LDO can speed up transient response.

The proposed current-mode low dropout voltage regulator has been fabricated in TSMC 0.35μm 2P4M CMOS process, the supplying voltage is 3V, the input current range is 185mA~350mA, the output voltage is 1.8V, and the max efficiency is 97.3%. The chip includes 1177 transistors and area is 0.783×0.875mm2.

並列關鍵字

Low Power-Bounce Current-Mode Low Dropout Voltage Regulator ； Power-Bounce；Ground Bounce；Quiescent Current

參考文獻

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