- 學位論文
10位元200MS/s切換電流式管線型類比數位轉換電路之佈局考量
Layout Consideration of the 10Bit 200MS/s Switched-Current Pipelined Analog-to-Digital Converter
摘要
本論文旨在以電路佈局方式來改善十位元之切換電流式管線型類比數位轉換電路之性能，並減少晶片面積，其重點在於改善類比電路的佈局規劃，特別就寄生效應、電源線寬度、雜訊防制、類比元件匹配及減少晶片面積等五個面向提出改善方法。 為了滿足電路10位元200 MS/s的高精確度與高操作速度，需針對各類比電路之功能做佈局考量，其考量因素為：取樣保持電路之元件匹配且類比輸入訊號、參考電壓必須與脈衝訊號隔離，其內部雙級運算放大器的被動元件(電阻電容)須選擇精準特性之元件；低輸入阻抗電流比較器電路之元件需匹配且類比輸入訊號、參考電壓必須與脈衝訊號隔離；數位類比轉換器電路之參考電壓必須與脈衝訊號隔離。 透過各類比電路之佈局規劃，再以相鄰元件佈線最短為依據整合，減少導線長度與寄生效應，並且電源線以金屬層並聯方式減少寬度，使得因導線與電源線所佔據的區域大大降低，如此可提升電路性能與降低晶片面積。再者，藉由減少電源線的長度，電壓降雜訊(IR-drop)也會比較小。完成所有佈局後，利用基底之零碎空間，加入P+摻雜並引入乾淨之接地電源線，藉此來減少類比電路受到數位電路的干擾。 另外，本論文採用TSMC 0.18μm 1P6M標準製程，以Calibre 萃取Layout RC值，並將改善前與改善後的電路功能做比較，確定改善前後的佈局差異能使電路之性能更優秀。改善後的核心晶片面積約為479x638μm 2為改善前之晶片面積的0.5倍。面積縮小50.5%性能提升359.25%
並列摘要
The thesis improves the performance of the switched-current pipeline analog-to-digital converter (ADC) using the layout consideration. The key merit is to decrease the chip area with layout technical. Furthermore , the parasitic effect , the width of power line width, the reduction of noise and component match of analog circuit are considered ,too. The destination not only enhances the performance of the pipelined ADC, but also to reduce the chip area. In order to meet the speciation with the solution of 10bits and the conversion rate of 200MS/s , there are four aspects must be considered : firstly, the matching of the sample and hold circuits ; secondly , the passive device must be selected more accuracy in two-stage operational amplifier , thirdly , the current comparator with low impedance must be emphasized and analog signal must be separated with the digital signal , finally the reference voltage of pipelined ADC must be separated with digital signal. In the layout plan , the minimized path between adjacent devices is considered; and that the shorter the width of power line is , the smaller the parasitic effect is . Moreover , all the power lines and established with metal layers parallel to reduce the metal width . The performance of the proposed pipelined ADC will be improved by eliminating the parasitic . effect and reduce the chip area . Furthermore , the noise voltage can be reduced by shortening the length of power line , and so does the IR drop. After finishing the whole chip layout and adding the P+ guard ring in the spare area , the wterference can be avoid fromtludigieal circuit .The TSMC 0.18μm 1P6M standard process is used to design and implement the proposed pipelined ADC in this thesis .According to the layout , the chip area can be improved and reduced to about 479x638μm 2. Which is roughly 0.5 times of that of traditional layout . The chip area is minimized to 50.5% and the performance can be improve to 359.25%