消除高密度腳位及多模組記憶匯流排之串音干擾及阻抗不匹配

在高密度腳位走線會造成多餘的串擾及不連續性，本論文提出簡化方程式用以評估串擾及不連續性所造成的影響。而為了評估在高密度腳位佈線所造成的誤差，我們利用了三維的模擬軟體模擬了在測試板上一部分的高密度腳位。其結果指出，其結果指出當寬度較寬的走線用於測試板上時會造成多餘的共振。而為了進一步評估測試線的特徵阻抗變化對於連接器特徵阻抗的影響，我們利用ADS模擬TRL的校準線。而相應於不同特徵阻抗走線的誤差模型可以從這些不同阻抗的TRL校準線萃取出來。我們進一步地在中央處理單元與多模組記憶匯流排的區域研究這些耦合所造成的影響。緊密排列的訊號線間彼此的耦合，其奇、偶模態下特徵阻抗的改變將導致阻抗不匹配，而這個問題會造成訊號被推動過度或是推動不足致使眼圖高度縮小。而訊號在奇、偶模態下的相速度不一致會導致訊號抵達接收端的相位不同步，而導致眼圖的寬度縮小。本論文中，利用兩個步驟來提升訊號完整性：首先，求出傳輸線的奇、偶模特徵阻抗並計算各端埠的散射參數，定義粒子群聚最佳化演算法的適應函數，反射量越小越好、傳輸量越大越好，藉由調整傳輸線特徵阻抗與終端電阻使各端埠阻抗匹配，改善推動過度與推動不足的情形；第二個步驟是減少眼圖的抖動，在相鄰線之間加入補償電容可降低奇模態的傳播相速度，使訊號抵達接收端的相位與偶模態接近，透過眼圖結果可證實粒子群聚最佳化演算法可有效的提升多模組記憶匯流排之訊號完整性。最後，訊號完整性的提升可以藉由散射參數及眼圖而得到驗證。

關鍵字

多模組記憶匯流排；訊號完整性；串音干擾；阻抗不匹配

並列摘要

Compact routing in a high density pin field results in artificial crosstalk and discontinuities. Simplified equations for the embedded and de-embedded processes are proposed for evaluating the errors caused by crosstalk and discontinuities. To evaluate the error caused by coupling due to routing on a high density pin field, a portion of the pin field of the test board is simulated by using the full wave solver. The simulation results indicate that significant artificial resonance occurs when wide traces are used in the board design. To study the effects of impedance variation, a TRL calibration kit without coupling effects is designed using ADS. The error boxes with different impedances can be extracted through post-processing with the TRL calibration kits. The high-density routing is further studied on the coupling impacts of the CPU and DIMM area. The high-density routing under the areas increases crosstalk and discontinuities, the original design of even and odd mode characteristic impedances changes. The occurrence of multi-drop problem between the CPU and memory chip causes over- and under-driven that reduce the eye opening. Furthermore, the different phase velocities of even- and odd-modes cause timing jitter at the receiver end. This dissertation proposes two steps to solve the complex issue of signal integrity for the multi-module memory bus. First, particle swarm optimization (PSO) is used to tune the characteristic impedance of the transmission line and on-die termination (ODT) values such that the variation of transmission line impedance can be improved and maximum power delivery can be obtained. The cost function of the algorithm is defined by selecting the minimum reflection coefficient at the driver side and maximum the transmission coefficient at the receiver side to reduce the over- and under-driven. Second, the timing jitter can be reduced by placing a capacitor to compensate for the velocity difference caused by different propagation modes. Finally, signal integrity enhancements for the DDR3 are verified by measuring S parameters in the frequency domain and post-processed eye diagrams in the time domain.

並列關鍵字

multi-module memory bus ； signal integrity ； particle swarm optimization

參考文獻

[1]. S. H. Hall, G. W. Hall, and J. A. McCall, High-speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, John-Wiley & Sons, 2000.

[2]. D. B. Lin, F. N. Wu, W. S. Liu, C. K. Wang, and H. Y. Shih, “Crosstalk and Discontinuities Reduction on Multi-Module Memory Bus by Particle Swarm Optimization,” Progress In Electromagnetics Research, vol. 121, pp. 53-74, 2011.

[5]. T.H. Kim, U.R. Cho, and H.G. Byun, “A 1.2V Multi Gb/s/pin Memory Interface Circuits with High Linearity and Low Mismatch,” IEEE Int. Conf. on Circuits and Systems, Vol. 2, pp.1847 – 1850, May 2005.

[6]. R. Das, J. Iyer, V. Suchitha, K. Praveen, Y. Minh Ti Tran, S.A. Thomas, S.K. Gupta, and, W. Kraipak, “Novel bus termination schemes to reduce IO power consumption on low power intel small form factor platforms,” Electronic Components and Technology Conference, pp. 521 – 525, May 2008.

[9]. Y. Liu, L. Tong, Y. Tian, and B. Gao, "Measurements of planar microwave circuits using an improved TRL calibration method," Progress In Electromagnetics Research, vol. 109, pp. 263-278, 2010.

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消除高密度腳位及多模組記憶匯流排之串音干擾及阻抗不匹配

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