微電鑄與研磨技術在覆晶凸塊與高頻探針針卡製作上的應用

The application of fabrication on flip chip solder bump and RF probe card by using micro-electroplating and polishing technologies

許后竣(Hou-Jun Hsu)

指導教授 ： 黃榮堂

國立臺北科技大學/機電學院/自動化科技研究所/碩士(2005年)

摘要

微電鑄技術是在微機電LIGA製程技術中唯一可以快速製造金屬微結構的製程。利用微電鑄技術可以批量生產高深寬比(High-Aspect-Ratio)或複雜形狀的3D微結構，可以降低成本、滿足市場的需求，這是微電鑄技術的一大特色。
然而微結構電鑄的品質及鑄層厚度的差異性，深受結構圖案設計、圖案密度、圖案分佈位置、深寬比及電鑄液組成、電流密度分佈成等因素的影響。為了使電鑄後的微結構高度均一及表面平滑，本文在光阻去除前使用一道研磨的製程，以改善微結構電鑄的品質及鑄層厚度的差異性。
本篇論文旨係將微電鑄技術與一種類似CMP的研磨技術運用在複雜形狀的3D微結構的製作上，其目的有二：第一，利用微電鑄技術製作覆晶凸塊，再利用研磨技術研磨凸塊，使凸塊的高度在迴銲前後達到一致性。最後期望在一4吋的晶圓上高度55 um未經迴銲的凸塊其均勻性可控制在 2.5 um以內，且在經迴銲後其均勻度可控制在4％以內，以改善後續封裝的品質。第二，使用多層式堆疊電鍍配合研磨技術與微裝配來製作高頻探針卡，使其具有較高的操作頻率，且製作容易的精密探針卡，使目前高價的高頻探針卡可降低其價格。

關鍵字

覆晶凸塊 ； 高頻探針 ； 微電鑄 ； 化學機械研磨

並列摘要

The micro-electroplating process is the only method that can fabricate metallic micro-structures speedy in the LIGA/MEMS technology. This kind of deposition method is characterized by manufacturing high aspect ratio and complex 3D structures easily, resulting in lowering process cost and meeting market requirements.
The quality and uniformity of the plated micro-structures, however, is frequently influenced by some factors such as pattern design, pattern allocation, pattern location, aspect ratio, compositions in the plating solution and current distribution during plating process. In order to acquire uniform thickness and smooth roughness after plating, we employ a polishing process to improve its quality and uniformity before stripping the photoresist.
The work of this study is to combine the micro-electroplating process with the polishing process on the fabrication of complex 3D microstructures. There are two focuses in this study. Firstly, we use a polishing process to polish plating-based flip chip solder bumps by which we can obtain high uniformity thickness no matter before and after reflow process. Afterward we are expected to have high assembly yield rate by precisely controlling the uniformity before reflow within 2.5 um on the solder bumps with 55 um height across the entire 4 inch wafer and the height uniformity after reflow can obtain as accurate as up to 4％ as a whole. On the other hand, using multi-layer micro-electroplating technology along with the same polishing process, we can fabricate high RF probe card featuring with high precision in dimension, excellent performance in high frequency and low cost in process as well.

並列關鍵字

Flip Chip Solder Bump ； RF Probe Card ； Micro-Electroplating Process ； Chemical Mechanical Polishing (CMP)

參考文獻

1. C. S. Chang, A. Oscilowski, and R. C. Bracken, "Future Challenges in Electronics Packaging", Circuits & Devices, 1998, pp.45~54.

9. J. H. Lau, Handbook of Tape Automated Bonding, New York：Van Nostrand Reinhold, 1992.

12. P. A. Totta and R. P. Sopher, "SLT Device Metallurgy and its Monolithic Extension", IBM J. Research Devel.,1969, pp.226~237.

13. P. Elenius, "Flex on Cap-Solder Paste Bumping", 3rd International Symposium and Exhibition on Advanced Packaging Materials, Processes, Properties and Interfaces, 1997.

14. T. D. Dudderar, "AT&T Surface uMount Assembly: A New Technology for the Large Volume Fabrication of Cost Effective Flip Chip MCMs", International Journal of Microcircuits and Electronic Packaging, Vol. 17, No. 4, 1994, pp.361~368.