使用插入延遲法分析晶片內部電源網格之功率完整性

Analyzing Power Integrity of On-Chip Power Grids by Using Latency Insertion Method.

柳柏任(Po-Jen Liu)

指導教授 ： 林丁丙

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2009年)

摘要

本論文在探討由於積體電路微小化以及工作時脈的增加的緣故，電路密集度增加、開關速度越快，產生更大的IR電壓降與切換開關雜訊 電壓變動，造成晶片內部的電源網格區域供應電壓之變動也越嚴重，大大地影響其功率完整性。因此先探討晶片內部電源網格結構特性，再使用插入延遲法(Latency Insertion Method, LIM)，模擬開關切換雜訊在時域上的影響。
多層的晶片內部電源網格結構，可由散射參數得到各層電源/地線的每單位長度之RLC傳輸線參數，並建立等效電路。本論文在模擬開關切換雜訊時依循兩個步驟：1)先使用修正節點分析法 (Modified Nodal Analysis , MNA)做直流分析，即開關未切換之前的靜態IR電壓降分析，2)接著再使用插入延遲法做暫態分析，計算開關切換雜訊發生時IR電壓降與 電壓變動。本論文主要分析開關切換雜訊發生在不同的網格尺寸、不同的疊層結構，所造成之區域供應電壓之變動，提出改善方法或維持其功率完整性的設計準則。

關鍵字

晶片內部電源網格 ； 功率完整性 ； 插入延遲法

並列摘要

Due to the miniaturization of integrated circuit and the clock frequency increasing, the density of circuit integration and the velocity of switching activity have been raised rapidly. Therefore, larger IR voltage drop and voltage fluctuation have been induced to affect the power supply fluctuation and the power integrity of On-Chip power grids significantly. In this paper, to analyze the issue mentioned above in detail, we first discuss the characteristics of On-Chip power grids, and then simulate the switching noise by using LIM at time domain.
In each layer of multilayer On-Chip power grids, the pre-unit-length transmission line parameters , R, L and C can be extracted from S-parameter to establish the equivalent circuit. In this paper, the switching noise simulation follows the two steps as follows: 1) Using MNA (Modified Nodal Analysis) for DC analysis, i.e. static IR drop analysis when switching noise has not occurred yet. 2) Using LIM for transient analysis to capture the IR drop and voltage fluctuation when switching noise occurs. In this paper, we discuss the power supply fluctuation under different conditions such as different dimensions of grid ,different layer configurations. Besides, we propose an approach to either improve or maintain the power integrity within specified design margins.

並列關鍵字

On-Chip Power Grids ； Power Integrity ； Latency Insertion Method

參考文獻

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