一個使用緩衝器插入且考量連線延遲的單源扇出最佳化

A Single Source Fanout Optimization Using Buffer Insertion Considering Interconnect Delay

吳國富(Kuo-Fu Wu)

指導教授 ： 李育民

國立交通大學/電機學院/電機學院IC設計產業專班/碩士(2010年)

https://doi.org/10.6842/NCTU.2010.00803

摘要

隨著半導體設備的複雜度持續的發展，電子設計自動化工具的效能及積體電路設計流程必須著重所有的奈米問題。緩衝器插入是用來改善時序問題效能先進科技技術。扇出最佳化在時序最佳化中是一個基礎的問題。在這篇論文中，我們採取緩衝器插入技術且考量連線延遲來解決單源扇出最佳化問題。

關鍵字

緩衝器插入 ； 扇出 ； 連線延遲

並列摘要

As the complexity of the semiconductor device continues to explode, the EDA tool performance and IC design flows are necessary to address all nanometer issues. Buffer insertion is the state-of-the-art technology, which is used to improve the performance of the timing issue. Fanout optimization is a fundamental problem in timing optimization. In this thesis, considering the interconnect delay , we will adopt the buffer insertion technique to
solve the single source fanout optimization problem.

並列關鍵字

buffer insertion ； fanout ； interconnect delay

參考文獻

[1] L. P. P. P. van Ginneken, “ Buffer placement in distributed RC-tree networks for minimal

[2] H. Bakoglu, “ Circuits, Interconnections, and Packaging for VLSI,” Addison-Wesley Publishing

[4] Weiping Shi and Zhuo Li, “ A Fast Algorithm for Optimal Buffer Insertion,” in IEEE

[5] Weiping Shi and Zhuo Li, “ An O(nlogn) Time Algorithm for Optimal Buffer Insertion,”

[6] Zhuo Li and Weiping Shi, “ An O(bn2) Time Algorithm for Optimal Buffer Insertion