目前無線射頻身份識別系統已相當普遍的應用於門禁等系統,但主要關鍵組件則均為國外大廠所掌握。在國內只有少數廠商有能力著手發展無線射頻身份識別系統相關組件,但在讀卡端積體電路化,還正處於發展階段。本論文將以0.35um CMOS製程來完成13.56MHz無線射頻身份識別系統讀卡機之設計,讀卡端以CMOS製程實現有低成本、方便電路整合、縮小電路體積等優點,可使無線射頻身份識別系統應用更為方便與廣範。 論文中對無線射頻身份識別系統工作原理分析,以設定讀卡機性能規格,同時對讀卡機的性能測試予以量化。所設計的讀卡機電路使用Hspice模擬分析後,透過國家晶片系統設計中心(CIC)的協助,使用台積電0.35um製程來實際製作此晶片, 同時以CMOS運算放大器完成相同的電路架構以驗證讀卡機晶片電路,並將所完成的讀卡機硬體電路予以完整正的系統性能量測。此晶片面積大小為0.880mm x 0.596mm。
Recently the RFID system have been applied in the safety system, but the key components of RFID system are always controlled by the national manufacturers. Only a few local manufacturers have the ability to develop RFID components. In this thesis we use 0.35um CMOS process to design the chip of 13.56MHz RFID reader. Low cost, high integration and compact size are the advantages of CMOS RFID reader. We have simulated the designed circuit of RFID reader by using the tool ’’Hspice’’. With the help of NSC Chip Implementation Center, we used TSMC 0.35um CMOS process to realize the circuit. We also realize the same designed circuit on the blackboard with CMOS OP-AMP. We measure the electric performance of this reader before IC processes. The chip size of the total circuit is about 0.880mm x 0.596mm.