使用虛擬路徑之帶通超取樣三角積分類比數位調變器

Pseudo-N-Path Bandpass ΣΔ A/D Modulator

陳超群(Chao-Chyun Chen)

指導教授 ： 吳紹懋

元智大學/工程學院/電機工程學系/碩士(2002年)

摘要

以三角積分(Σ∆)調變技術為基礎的超取樣帶通類比數位轉換器能夠有效數位化接收機在中頻部分的訊號。它有著不少的優點，如：較能被依賴，隨著製程能夠增加效能，並且還能有效降低低頻雜訊及避免直流偏移。
在本篇論文中，我們實現了一個較傳統調變器主動元件還要少的高速帶通三角積分調變器。論文中討論了虛擬路徑(Pseudo-N-Path)架構的二階帶通三角積分調變器。相較於傳統以利用交換電容(switched capacitor)雙迴路積分(biquadratic)濾波器為基礎的調變器有著更低的功率消耗。本論文採用0.35-µm CMOS 1P4M 製程實現一個利用虛擬路徑的帶通三角積分調變器。調變器由42.8MHz 的取樣頻率來達成在10.7MHz 中心頻率處,在200KHz 的頻寬內有43dB 的訊雜比。調變器在3.3V 的工作電壓下消耗功率為22mW。

關鍵字

調變器 ； 帶通 ； 超取樣 ； 虛擬路徑

並列摘要

Oversampled bandpass A/D converters based on delta-sigma modulation can be used to robustly digitize narrowband intermediate frequency (IF) signals for radios and cellular systems. It provides lots of benefits such as greater reliability, improved performance as technology scales,lowering low frequency noise and avoiding dc offset.
The implementation of a high-speed bandpass Σ∆ modulator with fewer active components is explored in this research. This thesis describes a pseudo-N-path (PNP) architecture for two-order, bandpass Σ∆ modulator that consumes less power than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the pseudo-N-Path topology has been integrated in a 0.35-µm, single poly,quadruple-metal CMOS technology with capacitors synthesized from a stacked-metal structure. The modulator, clocked at 42.8 MHz, digitalizes a 200-KHz bandwidth signal centered at 10.7 MHz with 43dB of dynamic range.
The experimental modulator dissipates 22 mW from a 3.3-V supply.

並列關鍵字

Modulator ； Bandpass ； Oversampling ； Pseudo-N-Path

參考文獻

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[7] Armond Hairapetain, ”An 81-MHz IF Receiver in CMOS,” IEEE J. Solid-State Circuits vol. 31, pp. 1981-1986, December 1999.