產生用於電腦輔助設計工具發展之合成邏輯網路

Generation of Synthetic Logic Networks for CAD Tool Development

徐禎堯(Jen-Yan Shiu)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2001年)

摘要

發展電腦輔助設計工具時，需要靠大量的測試電路來協助效能評估。然而，目前公開的測試電路，不是晶片面積過小，就是只為用來評估某種用途的電腦輔助設計工具而設計。本論文發展一個合成電路產生器來產生一些測試電路。這個合成電路產生器藉由真實電路的特性，如每個元件接腳數目的分佈、每條網路上元件接腳數目的分佈、每個元件面積大小的分佈等等，來產生合成電路。產生出來的合成電路，在組合邏輯元件間不存在回授迴圈，以及在最長路徑上的元件數目不會超過一個限定值。然而，有點超出我們期望的是，有一些合成電路竟然有很大的冷次(Rent’s)指數。這些使用我們自行設計的標準元件庫所產生出來的電路，會被用來產生被邏輯合成工具用來預估晶片繞線長度的繞線負載模式。但他的正確性卻不盡理想，我們相信這是那些冷次指數過高的合成電路所引起的。

關鍵字

電腦輔助設計 ； 測試電路 ； 冷次指數

並列摘要

Development of EDA tools needs a large number of benchmark circuits to evaluate the tools’ effectiveness. However, most of the existing circuits in the public domain are either of small size or designed for a particular purpose. In this thesis we develop a synthetic circuit generator that would use real circuit characteristics such as pins per cell, pins per net, size per cell distributions, etc. to generate synthetic benchmark circuits. The generated circuits are free from feedback loops and the number of logic cells on the longest path can be bounded by a specified number. However, it is somewhat out of our expectation that the circuits generally have a larger Rent’s exponent. The circuits have been applied to generate a wire-load model for an in-house standard cell library, but the accuracy in predicting wire length during logic synthesis is not good. We believe that this is caused by having a large Rent’s exponent of the synthetic circuits used in generating the wire-load model.

並列關鍵字

EDA ； benchmark ； Rent's exponent

參考文獻

[CBL] Computer-Aided Design Benchmarking Laboratory. URL:

[Iwa94] K. Iwama and K. Hino, “Random Generation of Test Instances for Logic Optimizers,” in Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 430-434.

[Iwa97] K. Iwama, K.Hino, H. Kurokawa, and S. Sawada, “Random Benchmark Circuits with Controlled Attributes,” in Proc. Eur. Design Test Conf., 1997.

[Hut97a] Michael D. Hutton, “Characterization and Parameterized Generation of Digital Circuits”, Ph D. Thesis, Graduate Department of Computer Science, University Of Toronto, 1997.

[Hut97b] M. Hutton, J. Rose, and D.Corneil, “Generation of Synthetic Sequential Benchmark Circuits,” in Proc. ACM/SIGDA Int. Symp. FPGA, Feb 1997, pp. 149-155.