具頻率域等化器的全數位單載波接收機之Top-Down設計及FPGA硬體實現

Top-Down Design and FPGA Implementation of an All-Digital Single-Carrier Receiver with Frequency Domain Equalizer

褚家興(Chu Chia Shing)

指導教授 ： 黃正光

元智大學/工程學院/通訊工程學系/碩士(2004年)

摘要

在本論文中,吾人採用一種由上至下(Top-down)之設計流程來實現一具頻率域等化器之單載波接收機(SC-FDE)。此種設計流程引入了兩種階層互動的概念。 在高階層的設計上，吾人使用Matlab來開發演算法及提升演算法之效能，而在較低階的RT/gate-level電路設計上，吾人使用Quartus II設計軟體和以Stratix EP1S25780C5 晶片為基礎的數位訊號處理發展版來做實現。此種方法提共了一種有效率的實現方式來完成一數位通訊收發機。
近年來的研究顯示，具有循環字首(CP)的SC-FDE系統將是多載波系統如正交分頻多工系統(OFDM)的強大對手。就像OFDM系統一樣，SC-FDE系統訊號傳輸也是使用結構式的方式，並且使用快速傅利葉轉換至頻率域做通道估測及等化。因此，此系統將會有和OFDM系統相似的效能及低的運算複雜度。然而相較於OFDM系統，由於單載波系統的低PAPR特性，在訊號傳輸功率上，此系統將會比OFDM系統有更好的表現。
在本論文中，主要呈現的結果是設計與實現操作在符碼傳輸率為1 Msps之QPSK-SC-FDE接收機的硬體架構。各部份的架構包括:升餘弦匹配濾波器(SRRC matched filter)，包封偵測機制(delay-and-correlation packet detector)，以CORDIC-based的載波頻率誤差估測機制，ROM-based的相位補償機制，FFT-based的通道估測及補償，和做相位追蹤的柯士達迴路。所有的硬體架構是使用Verilog硬體描述語言來撰寫，在Quartus II上設計與模擬，最後轉回Matlab來做驗證。配合使用64點的FFT，整體接收機總共使用Stratix 晶片27%的邏輯元件。此外一使用Farrow 內插的取樣時間同步器和二階柯士達迴路的T/2-spaced全數位QPSK接收機也將在此論文中提出及實現。

關鍵字

單載波系統 ； 頻率域等化器 ； 柯士達迴路 ； 硬體描述語言

並列摘要

In this thesis, we adopt a top-down design flow to implement an all-digital baseband receiver for single-carrier modulation with frequency-domain equalization (SC-FDE). Such a flow involves close interaction between two levels of design abstraction. The top-level design is based on Matlab for developing algorithms and performance evaluation, while the lower RTL/gate-level design is based on the Altera powerful Quartus II EDA software and the Stratix EP1S25780C5 DSP Development board. It is shown that the design paradigm provides a very efficient way to implement a digital communication system.
Recent researches show that the SC-FDE system with cyclic prefix (CP) is a promising competitor of OFDM system. Like OFDM system, it is a block-based transmission system using FFT algorithm for channel estimation and equalization. Hence it possesses the similar performance and low complexity advantages as OFDM. However, its transmitter has a higher power efficiency due to the low PAPR characteristics of the transmitted SC signal.
The major effort of this thesis is to design all the hardware modules for a QPSK-SC-FDE system operating at a symbol rate of 1 Msps. These modules include the square-root raised cosine matched filter, delay-and-correlate packet detector, the CORDIC-based carrier offset estimator, the ROM-based phase derotator, the FFT- based channel estimator and equalizer, and the recursive Costas loop for phase tracking. All the hardware modules are designed in Verilog HDL and back-annotated to Matlab for verification. With 64-point FFT, the hardware occupies about 27 % of the Stratix chip. Besides, an accompanying T/2-spaced all-digital QPSK receiver with Farrow interpolation timing synchronizer and 2nd-order Costas loop is also presented.

並列關鍵字

SC-FDE ； Frequency domain equalizer ； Costas loop ； FPGA implementation ； Top-down Design ； Verilog HDL

參考文獻

[3] C. Chien, Digital Radio Systems On A Chip, Boston, Kluwer Cademic Publishers, 2001.

[4] Erup, L.; Gardner, F.M.; Harris, R.A., “Interpolation in Digital Modems─Part II: Implementation and Performance,” IEEE Transactions on Communications, June 1993 Pages:998 — 1008.

[6] Yik-Chung Wu; Tung-Sang Ng, “FPGA implementation of digital timing recovery in software radio receiver”, Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on Circuits and Systems, 4-6 Dec. 2000, Pages: 703 — 707.

[9] Czylwik, A., Synchronization for single carrier modulation with frequency domain equalization, Vehicular Technology Conference, 1998. VTC 98. 48th IEEE , Volume: 3 , 18-21 May 1998, Pages:2277 - 2281 vol.3.

[13] U. Meyer-Baese, Digital Signal Processing with Filed Programmable Gate Arrays, Berlin, Springer, 2001.