應用於IEEE 802.11a WLAN之5.8-GHz CMOS射頻接收機前端電路

A 5.8-GHz CMOS RF Receiver Front-End for IEEE 802.11a WLAN Applications

林昀賢(Yun-Hsien Lin)

指導教授 ： 吳紹懋 博士

元智大學/工程學院/電機工程學系/碩士(2004年)

摘要

在本論文中一個應用於IEEE 802.11a WLAN之5.8-GHz CMOS射頻接收機前端電路被分析、設計並以聯電0.18um 1P6M CMOS製程實現。為了能達到高度整合的目的，此射頻接收機採用直接降頻式架構來設計，並整合了一個全差動低雜訊放大器、一個主動雙平衡式混頻器和一個小數-N頻率合成器。另外，考量低成本與低功率損耗的目的，此小數-N頻率合成器整合一個低功率高效率壓控振盪器、一個入射鎖定頻率除頻器和一個全數位管線化三階的MASH三角積分調變器。整個接收機前端電路能提供16.5dB的順向增益(Forward Gain)、5.4dB的雜訊指數(Noise Figure)、-10.2dBm的輸入P1dB及-9.3dBm的輸入三階交叉點(IIP3)，並且使用一個1.8V的電源供應整體功率損耗約48mW。
兩個5.8-GHz壓控振盪器測試晶片量測結果也附於本文中，晶片分別以聯電0.18um CMOS製程及台積電0.25um CMOS製程實現，量測結果顯示此兩個壓控振盪器在相對主頻率1MHz偏移量時，分別可達最佳約-100dBc/Hz及-95dBc/Hz的相位雜訊表現。

關鍵字

射頻接收機 ； 頻率合成器 ； 低雜訊放大器 ； 混波器 ； 壓控震盪器

並列摘要

In this thesis, a 5.8-GHz CMOS RF Receiver Front-End for IEEE 802.11a WLAN applications was analyzed, designed and implemented in UMC 0.18um 1P6M CMOS process. In order to achieve high integration, the RF receiver design was based on the direct-conversion architecture; it also integrates a differential low noise amplifier, an active double balanced mixer, and a fractional-N frequency synthesizer. Furthermore, in consideration of low cost and low power, the fractional-N synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider (ILFD) and a digital pipelined third-order MASH delta-sigma modulator together. The receiver has forward gain of 16.5dB, noise figure of 5.4dB, input P1dB of -10.2dBm and IIP¬3 of -9.3dBm, while the total power consumption is 48mW from a single 1.8V supply.
Some measurement results of two different VCOs testing prototype are also presented. They were fabricated by UMC 0.18um and TSMC 0.25um CMOS process, the measurement results of phase noise performance is -100dBc/Hz and -95dBc/Hz at 1MHz offset from the center frequency.

並列關鍵字

Receiver ； CMOS ； frequency synthesizer ； LNA ； mixer ； VCO

參考文獻

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