採用DS-MBOK系統之雙向決策回授多用戶系統FPGA硬體實現

FPGA Implementation of Bi-Directional Decision Feedback Multiuser Detection for DS-MBOK CDMA System

陳佩鴻(Pei-Hong Chen)

指導教授 ： 黃正光

元智大學/電機通訊學院/通訊工程學系/碩士(2009年)

摘要

本論文中，吾人採用一種由上層演算法至下層硬體架構實現此一新提出之具雙向回授之多用戶接收快速演算法硬體驗證流程，利用Xilinx FPGA發展平台及IP-based硬體架構設計軟體SystemGenerator，使用者可快速驗證其演算法於相對應硬體架構下之結果，有效縮短硬體定點運算結果產生之流程，此流程更可產生相對應之Verilog硬體語言，下載至FPGA版中，實際產生訊號以供儀器觀測及紀錄。
本論文首先描述一種用於多用戶上鍊環境中，直接序列M元正交鍵移(Multi-user DS-MBOK)系統下之高效率多用戶偵測接收機，其利用雙向決策回授機制，可於符碼速率下消除前、後符碼間干擾項(pre/post-cursor ISI)、展頻碼間干擾(MCI) 以及多用戶下之多重接取干擾(MAI) 之現象。其實驗結果可有效逼近單用戶匹配濾波器性能邊界之最佳性能。此外本論文中，吾人將更進一步提出設計相對應之發射機及多用戶偵測接收機硬體架構設計，並著重於運算複雜度簡化以及硬體資源節省等方面，如MBOK符碼映射及調變、多用戶雙向決策回授系數產生器、干擾扣除項產生器等需複雜計算及大量乘法器之部分，為提升系統整體操作時脈，吾人進一步採取多種縮短關鍵途徑(critical path)的方法於上述多用戶偵測接收機硬體架構設計中。最後將Matlab浮點模擬結果以及SysGen定點模擬結果進行性能比較，並利用示波器及邏輯分析儀等儀器實際紀錄及分析實現之系統性能。並進一步探討，類比數位轉換器(A/D converter)及接收機內部架構所使用之傳輸資料位元寬度(Inner word-length) 對整體性能及系統資源佔用之影響，以期在系統資源及性能之間找到最佳之系統參數。

關鍵字

M維二相正交鍵 ； 直接序列展頻 ； 多用戶偵測 ； 回授決策 ； FPGA 硬體實現

並列摘要

In this thesis, we adopt a Top-Down design flow to realize a newly proposed RAKE-BDDF MUD algorithm in hardware rapidly. By using the Xilinx FPGA development platform and IP-based EDA tool SystemGenerator (SysGen), the user can verify the hardware design of the algorithm and the fixed-point result without annoying Verilog programming, these shortening the duration form algorithm to hardware implantation. The SysGen can also generate the Verilog for downloading the FPGA board to generate the real-world signals which can be measured by oscilloscope and logic analyzer.
First, we present a highly efficient multi-user detection (MUD) receiver for Direct-Sequence M-ary Bi-orthogonal Keying (DS-MBOK) CDMA up-link system. By employing a double-round decision-feedback interference cancellation scheme with RAKE receiver, called multi-user bi-directional decision feedback (MU-BDDF), the RAKE-BDDF MUD receiver can cancel all the post-/pre- inter-symbol interference (ISI), multi-code interference (MCI) and multiple access interference (MAI) terms. The simulation result shows that the RKAE-BDDF MUD receiver can significantly improve the performance and approximately attain single user matched filter bound (SU-MFB). After the algorithm design, we present the hardware implementation for the DS-MBOK CDMA up-link system for the 2-user case. We focus on the aspect of complexity-reducing and resource-saving in structural design for all blocks in RKAE-BDDF MUD receiver, especially in coefficient generator and interference cancellation terms generator in MU-BDDF blocks, which require plenty of multipliers. To improve the system operating clock, we also consider several schemes to shorten the critical path in receiver. Finally, we compare the Matlab floating-point simulation results with the SysGen fixed-point simulation results and observe the signals with instruments. Some comparisons are also made for investigating the effect of the codeword length of A/D converter and the internal data bus width in receiver blocks to find out the best parameters such as to balance the system recourse and performance.

並列關鍵字

DS-MBOK ； CDMA ； multi-user detection ； decision feedback ； FPGA implementation

參考文獻

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