充分利用電路中必要之反閘改善連線延遲

Using Essential Inverters for Interconnect Delay Reduction

李隆仁(Lung-Jen Lee)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2006年)

https://doi.org/10.6838/YZU.2006.00004

摘要

隨著電晶體製造技術不斷創新，影響整體電路性能表現之主要因素已逐漸轉為電路中的連線延遲大小。這個問題的有效解決方案之一便是在適當位置”置入緩衝器” 。然而，增加緩衝器雖然有助於減少電路連線延遲，但同樣的也增加了整體電路使用的面積大小、功率消耗並增加電路壅塞程度。本研究目的在探討如何充分利用必要之反閘在電路中的推力來改善電路連線延遲的問題並有效減少緩衝器的使用量。必要的反閘乃在能使電路產生正確功能。刪除任何一個反閘將會導致電路的錯誤。大部分的必要反閘屬於同向閘，如AND，OR等。
以較大型電路如ITC99’而言，本研究所提方法相較於未利用必要反閘的方法，在時效性上有0.78%至4.90%的改進幅度，而對於較小型電路如ISCAS89’則無明顯改善。

關鍵字

反閘 ； 連線延遲 ； 緩衝器

並列摘要

With the advance of VLSI process technology, interconnect delay increasely dominates the circuit performance. Buffer insertion is one of the crucial approaches to this problem. However, buffer insertion not only increases total chip area but also increases power dissipation. In this thesis, we propose to use essential inverters to reduce the use of buffers. An essential inverter is an inverter required to make a circuit function correctly. Removing of any essential inverters will result in malfunctioning of a circuit. Most of the essential inverters are embedded in positive unate gates such as AND, OR etc. In our experiment, we extract essential inverters from positive unate gates.
Compared to without using essential inverters, our approach results in 0.78% to 4.90% timing improvement on ITC99’ benchmark circuits with larger sizes while no improvement on ISCAS89’ benchmark suits with smaller sizes.

並列關鍵字

inverter ； interconnect delay ； buffer

參考文獻

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