- 學位論文
一個基於結構化客製晶片並用於可程式化鑽孔之繞線結構的繞線器
A Router for Structured ASICs with Via Configurable Routing Fabric
摘要
可結構化客製晶片被使用來填補標準化客製晶片和FPGA之間的鴻溝。在過去，針對具有事先定義的繞線結構之可結構化客製晶片的繞線器並沒有受到應有之研究。在此篇論文中，我們針對可結構化客製晶片提出一個繞線器。我們的繞線器與其所用之繞線結構是互相獨立的。我們的繞線器主要分成以下幾個部分。一個用來把繞線結構轉換成繞線圖的繞線圖產生器。一個基於Dijkstra最短路徑演算法的multilevel routing。一個用於完成先前沒有完成繞線的rip-up和reroute的步驟。我們也設計一個語言去描述繞線結構。我們的繞線器整合至Synopsys和Cadence的標準化客製晶片工具來形成一個可結構化客製晶片之設計流程。實驗結果顯示，我們的繞線器可以100%完成ITC’99測試電路之繞線（最高到16900條線路和21100個邏輯閘）。就我們所知，我們是第一個學術研究團隊擁有此類之繞線器。之後，我們將針對大型電路去減少我們繞線器的執行時間。
並列摘要
Structured ASIC design methodology is invented to fill the gap between standard cell design and FPGA. Router for Structured ASIC designs with pre-defined routing fabric was not well investigated in the past. In this thesis, we proposed to develop a router for Structured ASICs. Our router is made to decouple from the underlying routing fabric. It has the following major components. A routing graph creater transforms routing fabrics into a routing graph. A multilevel routing approach based on Dijkstra shortest path algorithm that creates a route for each connection between two terminals. A rip-up and reroute procedure which completes the routing of nets that are not routed successfully in the previous step. As a by product, we also design a language to describe a routing fabric. Our router is integrated into a design flow based on Synopsys and Cadence tool sets for standard cell design. Extensive experiments performed for some of ITC’99 benchmarks show that our router can achieve 100% routing of these benchmarks (up to designs with 16900 nets and 21100 gates). To the best of our understanding, our router is the first of its kind done by an academic research group. In the future, we would like to reduce the run time required by our router for large designs.