In this thesis, we propose the implement of multimedia digital image processing module using partial reconfiguration method, we choose discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) as the example, the use characteristic of the matrix transpose to build a architecture easier using partial reconfiguration implement discrete cosine transform and inverse discrete cosine transform. we use the Verilog HDL within Xilinx ISE 9.2i design tool to complete this architecture. After that, we use FPGA for function simulation and verify computation data