在現今的硬體IC〈Integrated Circuit〉產業中,ASIC〈Application Specific Integrated Circuit〉仍然是主流架構。原因不外乎是其運算速度快、體積小、耗電量低等特性。但是ASIC只能一次燒錄的特性,使得在產品更新與修改上有著重大的缺失。所以運用可重複燒錄的可程式數位邏輯元件,如FPGA〈Field Programmable Gate Array〉,來設計晶片硬體架構,可增加產品功能上的彈性以及硬體的重複使用率,並延長產品的壽命。 因此本論文提出一個可重組態影像處理功能模組的硬體架構設計,將影像壓縮技術中的DCT〈Discrete Cosine Transform〉與IDCT〈Inverse Discrete Cosine Transform〉設計成可重組態的功能模組,使其可動態置換影像壓縮的功能模組,進而加強了影像壓縮的功能性、擴充性,也提昇了硬體資源的重複使用率,減少硬體資源的浪費,另外也降低了傳統設計上的複雜度以及開發時間與成本。
Within the hardware IC (Integrated Circuit) industry, ASIC (Application Specific Integrated Circuit) is still the main stream among all. The reasons for this are nothing but the fast speed of number crunching, small volume and low electricity requirement. However, the specialty of one-time burning had made serious flaw on the product’s updating and adjusting. Thus, by applying reburnable program digital logic units, like FPGA (Field Programmable Gate Array), to design the chip’s hardware framework, we can improve the flexibility of products’ function and the repeated usage of the hardware and the extension of the products’ usage duration will be done. Thus, within the present thesis, a design of hardware framework which allow reconfigurable function module of image processing coder is proposed. We choose the DCT〈Discrete Cosine Transform〉and IDCT〈Inverse Discrete Cosine Transform〉and design them into reconfigurable function modules, so that it can dynamically replace the function module of image processing coder. This will improve the ability and the expandiblity of the image processing coder. Also it can enhance the repeated usage percentage of the hardware resource and reduce the waste of it. Furthermore, the reconfigurable function module design method will reduce the complexity and the development duration and cost comparing with the traditional industry.