- 學位論文
應用於UWB接收機射頻前端積體電路之研製
The Design and Implementation of RF Receiver Integrated Circuit for UWB Applications
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摘要
本論文提出一全積體化之UWB 接收機射頻前端積體電路之研製，使用TSMC 0.18 μm 1P6M CMOS製程實現，可應用於UWB低雜訊放大器及混頻器之設計。UWB系統是一無線網路技術，能在低功率消耗之條件下，於短距離內達到高速無線寬頻傳輸；本低雜訊放大器設計符合UWB(IEEE 802.15.3a)從3.1到10.6 GHz之頻段。並透過國家晶片系統設計中心 (CIC) 之協助，完成此晶片之製作。由於傳統設計寬頻放大器大多使用晶片面積或功率消耗較大的架構，因此本論文以CG方式作為RF輸入匹配網路，減少使用多電感作為寬頻匹配而造成晶片整體面積較大；因使用單一電感做匹配，因此縮小了晶片面積，此晶片面積大小為0.5mm2。另外將此匹配網路配合RC回授電路及中間級電感的疊接放大級，設計出3.1~10.6GHz低雜訊放大器，在整個寬頻帶中，可獲得較佳的增益平坦度。 另外提出使用CG之匹配網路作為雙輸入之方式，設計一含3~11GHz頻段之寬頻混頻器；因使用單一電感作為匹配，因此可縮小晶片面積。經模擬結果，其操作頻率為3~11GHz，轉換增益大於6dB，雜訊指數為5.9~8.2dB，P1dB為-19.5dB，IIP3為-9.5~-8.0dB，消耗功率14.7mW。
並列摘要
This thesis proposed for the developments of receiver RFICs for Ultra-wide-band UWB system with the TSMC 0.18um 1P6M CMOS process. The designed ICs for the low noise amplifier (LNA), down-convert mixer applications. UWB systems are an emerging wireless technology capable of transmitting data over a wide frequency band for short ranges with low power and even higher data rate. The allocated band of UWB (IEEE 802.15.3a) is between 3.1–10.6 GHz. The designed is also supported by the chip implementation center (CIC). Due to the traditional designs of UWB LNAs usually consume plenty of chip size and power, thus we proposed a input matching network that with common-gate and utilizes an inductor in it, so it can reduce the utilization of chip area. The total chip size with pads was 0.5mm2. In addition, the matching network cooperates with RC feedback circuit and a cascade amplifier with an inter-stage inductor. In the design of 3-6 GHz low noise amplifier, the designed in-band gain of UWB mode can be flat. Over and above, we proposed a mixer with a common-gate (CG) matching network. The operated frequency was 3-11GHz; Due to the matching structure only use single spiral inductor, so the utilization of chip area can be reduced. The simulation performances are as follows: the bandwidth 3 ~ 11 GHz, gain is above 6 dB, noise figure in 5.9~8.2 dB, P1dB gain-compression point in ????5 dBm, and the input third- intercept-point in about -9.5~8.0 dBm, the dissipated power was 14.7mW.
參考文獻
[1] “An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-μm CMOS,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 3, MARCH 2007
[4] 張恩瑞，「UWB無線通訊接收機射頻前端電路研製」，碩士論文，元智大學，通訊工程學系，2006.
[5] Shih-Chih Chen, Ruey-Lue Wang, Ming-Lung Kung and Hen-Cho Hung, “An Integrated CMOS Low Noise Amplifier for Ultra wide Band Applications,” IEEE International Conference on Wireless Network, Communications and Mobile Computing, 2005, Vol.2, pp.1354-1357.
[6] Ruey-Lue Wang, Min-Chuan Lin, Cheng-Fu Yang, Chih-Cheng Lin, “A 1V 3.1~10.6GHz Full-band Cascoded UWB LNA with Resistive Feedback,” IEEE 2007.
[7] Chih-Fan Liao, Shen-Iuan Liu, “A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers,” IEEE Journal of Solid-State Circuits, vol.42, no.2, pp.329-339, Feb.2007.