結構化客製晶片之繞線結構的設計與分析

Design and Analysis of Via Configurable Routing Fabrics

蔡欣霈(Hsin-Pei Tsai)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2012年)

https://doi.org/10.6838/YZU.2012.00015

摘要

積體電路(IC)的製程越來越先進，在設計IC時要處理的問題也越來越困難。一般來說，一個晶片製程需要多個光罩，而製造光罩的費用由於製程技術的精進，而變得越來越昂貴。為了降低製造晶片的成本，又不失其效能，於是在半導體產業中出現了可結構化客製晶片(Structured ASIC)的技術，它在專用集成電路(ASIC) 與現場可編程門陣列 (FPGA)的中間地帶佔有一席之地，成為不容忽視的一項晶片製造技術。可結構化客製晶片是由一些預製的電晶體、事先定義完成的金屬層，和尚未定義的鑽孔(via)層(或少許金屬層)組成，稱為可配置導孔邏輯區塊(via-configurable logic block, VCLB)，設計者僅需製作鑽孔(via)層光罩便可完成基本邏輯設計，而且可平分預製的光罩費用來降低成本。可結構化客製晶片的繞線器是可結構化客製晶片中的一個重要工具，而可結構化客製晶片的繞線器使用可配置導孔繞線結構(via-configurable routing fabric, VCRF) 繞線，因此有一個好的可配置導孔繞線結構便十分重要。本論文提出了一個方法對可配置導孔繞線結構進行設計與分析，我們發現，分析繞線時的線長(wire length)以及穿孔數(via count)是評估繞線結構優劣的一個很好的指標。我們也進一步評估當一個global bin出現內部連線(internal nets)時，對繞線資源造成的影響。我們使用這個指標成功設計出好的可配置導孔繞線結構。

關鍵字

結構化客製晶片 ； 可配置導孔繞線結構

並列摘要

With the advances in integrated circuit(IC) technology, the costs of designing and manufacturing ICs increase dramatically. Since a chip consists of numerous pattern formational layers, mask cost becomes very large for an advanced manufacturing process. To reduce IC design and manufacturing cost, structured ASIC emerges as a new design alternative. Structured ASIC consists of prefabricated transistors and prefabricated masks for some metal layers, and a few un-customized mask layers for vias. The logic in a structured ASIC is implemented using a basic logic block called via-configurable logic block (VCLB). The designers need only to customize a few via masks to complete the logic implementation and share the prefabricated mask cost. Structured ASIC router is an important tool to via-configurable structured ASICs. A structured ASIC router employs a via-configurable routing fabric (VCRF) to complete routing. Without such a router, structured ASIC will not become a viable technology. In this thesis, we present a method for design and analysis of VCRFs. We find that the trade-off between wire length and via count is a good metric for qualifying a VCRF. It can be used along with the degree of reduction in average routing resource per internal net in a VCRF to determine which VCRF is better. This metric is validated by full-chip routing and has been successfully used to create better routing fabrics.

並列關鍵字

Structured ASIC ； via-configurable routing fabric

參考文獻

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