壹保護積體電路之靜電放電抑制器的性能改善

Performance Improvement of an ESD Suppressor for IC Protection

李培堃(Pei-Kuen Li)

指導教授 ： 陳興義

元智大學/電機通訊學院/通訊工程學系/碩士(2013年)

https://doi.org/10.6838/YZU.2013.00200

摘要

本論文利用時域有限差分法去模擬計算一個靜電放電抑制器在填充空氣、氖氣、氬氣和氦氣四種不同氣體條件下的電容、電荷、觸發電壓、箝制電壓、靜電放電電流以及最大電場。為了驗證時域有限差分法之準確性，靜電放電抑制器的模擬電容值利用電容量測及時域貫量法所模擬之電容值加以檢驗，檢驗結果發現它們之間的電容值非常吻合。研究中發現在相同結構的條件下，將空氣置換為氖氣、氬氣和氦氣所模擬得到的電容值並無明顯差異，但在填充空氣的靜電放電抑制器中，具有比其他三者惰性氣體氖氣、氬氣和氦氣高出許多的觸發電壓和箝制電壓。另外也發現尖端放電間距或者是操作頻率的增加，皆造成電容值變小。但靜電放電抑制器基板(Substrate)或是保護層(Overcoat)的相對介電常數變大會使電容值變大。靜電放電電流的波型會產生暫態現象且電流在極短的時間內達到最大值，當時間持續增加時，電流值會迅速地衰退。時域有限差分法亦被利用來研究模擬靜電放電抑制器填充四種不同氣體空氣、氖氣、氬氣和氦氣之輻射電場，研究中發現最大輻射電場值存在靜電放電抑制器的放電間隙中，在尖端放電間隙之外，雖然最大電場皆低於氣體崩潰電場，但電場值仍然是非常可觀，在靜電放電抑制器2 mm的範圍內仍舊有極大的輻射電場，因此本文建議在積體電路的設計以及電子元件的編排位置上至少應距離靜電放電抑制器1 cm以上以確保不會發生電磁干擾現象。

關鍵字

電容 ； 觸發電壓 ； 靜電放電電流 ； 靜電放電抑制器 ； 時域有限差分法

並列摘要

The finite-difference time-domain (FDTD) method was used to study the charge, capacitance, trigger voltage, clamping voltage, ESD current, and electric field of an ESD suppressor filled with air, neon, argon, and helium under different conditions. The obtained capacitance of the ESD suppressor filled with air under the condition of a spark gap distance of 5 m was validated by measurement data and another numerical result obtained by time-domain moment method (TDMM). Under the same conditions, it makes no big difference among the obtained capacitances for the ESD suppressor filled with air, neon, argon, and helium. But the ESD suppressor filled with air has much higher trigger and clamping voltages than the ESD suppressor filled with neon, argon, or helium. It is found that the capacitance decreases with increasing the spark gap distance or the operating frequency. But the capacitance increases with increasing relative dielectric constant of the substrate or the overcoat. It is observed that ESD currents with a transient waveform reach a maximum value in a variety of 3.2-5.6 mA at 0.9 ns and decays sharply as the time increases under the condition of the spark gap distance of 5 m. Outside the spark gap, the maximum electric field is below the breakdown strength, but the magnitude of the electric field resulted from ESD events is still very large as the distance from the ESD suppressor is less than 5 mm. Therefore, it is suggested that the ESD suppressor should be placed at least 1 cm away from high sensitivity electronic circuits.

並列關鍵字

Capacitance ； trigger voltage ； ESD current ； ESD suppressor ； FDTD

參考文獻

[3] C. Grewing, K. Winterberg, S. Waasen, M. Friedrich, G. Puma, A. Wiesbaue, and C. Sandne,“Fully integrated distributed power amplifier in CMOS technology, optimized for UWB transmitters,”Proc. IEEE Radio Frequency Integrated Circuits Symp., 2004, pp.87-90.

[4] C. Y. Lin, M. D. Ker, and G. X. Meng,“Low-capacitance and fast turn-on SCR for RF ESD protection,”IEICE Trans. Electron., vol. 8, pp. 1321-1330, Aug. 2008.

[5] M. D. Ker and C.Y. Lin,“Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs,”IEEE Trans. Microwave Theory Tech., vol. 56, no. 5, pp. 1286-1294, May 2008.

[6] M. D. Ker and W. J. Chang,“ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers,”IEEE Trans. Electron Devices., vol. 55, no. 6, pp. 1209-1416, June 2008.

[7] M. D. Ker and C. C. Yen,“Transient-to-digital converter for system-level electrostatic discharge protection in CMOS ICs,”IEEE Trans. Electromagn. Compat., vol. 51, no. 3, pp. 620-630, Aug. 2009.