輸出入緩衝器覆晶式設計在靜電防護上的分析與改進

On analyzing and Improving ESD protection in Area-I/O Flip-Chip Design

梁以正(Yi-Cheng Liang)

指導教授 ： 陳宏明

國立交通大學/電機學院/電機學院電子與光電學程/碩士(2011年)

https://doi.org/10.6842/NCTU.2011.00938

摘要

現今電子產品需求注重多功能與輕薄短小。因此，半導體封裝也朝高密度技術方向發展，而在高密度的微系統設計與封裝技術中，覆晶技術(Flip-Chip)已是一項成熟的方式，其重疊結構更利於IC積體化，垂直連接而非打線的方式也可減少連線距離，進而在高頻、雜訊和功率消耗上得到改善。在超大型積體電路設計中，設計者對於輸出入埠(In/Out ports)依然使用傳統環型結構(I/O ring)，它雖擁有成熟的靜電防護機制，卻增加了繞線距離，這份取捨也犧牲了原有的好處。

本文試著使用區域型輸出入元件(Area-I/O cell)配合新分佈架構去含蓋雙方優點，分析數據證明新架構在靜電防護能力上有大幅的提升，而新的排列方式在此架構上也有較佳的效果。最後此方法設計時亦考量一般設計者工作流程和習慣，實務上可輕易導入此機制。

關鍵字

輸出入緩衝器 ； 靜電防護 ； 覆晶式設計

並列摘要

Now the demands of electrical product are multi-function, lightweight and low profile. Based on this concept, the package methods have to meet high density trend. Flip-chip is a mature technology on high density microsystem design and packaging. This structure using vertical connection to substitute bonding wire can reduce the connection distance to get the benefits: high frequency demand, better noise control and less power consumption on metal. In general VSLI design, the circuit designers still use the I/O ring for chip design. The conventional I/O ring is the mature structure for ESD protection, but it increases the distance of connection. This trade-off loses the benefit from reducing the connection distance.

In this study, we try to use the new I/O distribution structure by Area-I/O cell to keep the two benefits. In our analysis, this new method has a large improvement for ESD protection. And new algorithm of cell assignment on this structure can obtain better result than general assignment method. Finally, we consider the present VLSI design flow in this discussion. New method can be easily applied in the original working flow.

並列關鍵字

Area-I/O ； ESD protection ； Flip-Chip Design

參考文獻

[1] J.-W. Fang, and Y.-W. Chang, “Area I/O flip-chip routing algorithm for chip-package co-design, ” Proc. of ICCAD, pp.518-522, 2008.

[2] J.-W. Fang, D. F. Wong, and Y.-W. Chang, “Flip-chip routing with unified area-I/O pad assignments for package-board co-design,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 336--339, San Francisco, CA, July 2009.

[3] J.-W. Fang , I.-J. Lin , P.-H. Yuh , Y.-W. Chang and J.-H. Wang “A routing algorithm for flip-chip design”, Proc. IEEE/Assoc. Computer Machinery Int. Conf. Computer-Aided Design, p.753 , 2005.

[4] R.-J Lee, and H.-M. Chen, “Algorithms for Chip-Package-Board Co-design ", PhD. Dissertation, National Chiao Tung University, 2011

[5] S. Voldman, John Wiley & Sons, “ESD : Circuits and Devices, ” 2006.