應用粒子群演算法於晶粒尺寸設計最佳化之研究

Applying particle swarm optimization approach for optimizing design of chip size

邱仕彰(Shih-Chang Chiu)

指導教授 ： 許嘉裕

元智大學/資訊學院/資訊管理學系/碩士(2013年)

https://doi.org/10.6838/YZU.2013.00267

摘要

半導體晶圓為了維持競爭優勢，晶圓廠需要盡可能增加每片晶圓上的晶粒數來降低生產每片晶圓的平均成本。目前已有最佳化晶圓曝光方法，在給定晶粒尺寸下使晶圓的晶粒數量最佳化。另一方面，提高單位每小時的晶圓產出也是生產重要的課題。晶圓光罩曝光次數所需時間，如果用較少的曝光次數完成整片晶圓曝光，將能有效減少生產之時間成本。然而，既有的研究多僅針對提升總晶粒數或減少曝光所需照射次數進行改善，鮮少有研究同時考慮。本研究提出兩階段粒子群最佳化演算法（two-phase non-dominated sorting particle swarm optimization, TNSPSO），利用粒子群演算法結合非支配解快速排序法，在一階段利用支配粒子快速搜尋邊緣解，在第二階段利用菁英的邊緣解快速彌補邊於多的空隙，改善PSO的粒子修正方法，能夠快速地找到柏拉圖最佳解，可在不增加生產費用同時增加最佳化晶圓曝光總晶粒數與光罩曝光的照射次數，有效的降低晶圓曝光時的生產成本。為驗證方法之效度，本研究先利用5組數值資料並與非凌略排序基因演算法（non-dominated sorting genetic algorithm II, NSGA-II）、多目標粒子群演算法（multi-objective particle swarm optimization, MOPSO）比較，實驗結果發現所提出的TNSPSO能夠快速的搜尋到問題的柏拉圖最佳解，實驗並考慮晶圓廠的曝光條件，比較方法的實際可行性結果，實驗發現TNPSO不僅能夠有效提升總晶粒數量以及降低光罩照射次數，且可以找到比NSGA-II、MOPSO更好的晶粒設計組合，證明本研究為有效之方法。

關鍵字

晶粒尺寸 ； 晶圓曝光效益 ； 粒子群最佳化 ； 柏拉圖最佳解 ； IC設計

並列摘要

In order to enhance the competitive advantages of wafer fabs, it is crucial for wafer fabs to increase the number of gross dies per wafer to reduce average die cost through productivity improvement.Most of studies focus on yield enhancement, yet little research has been done on cost reduction through increasing gross die number and decreasing shot number simultaneously due to the lack of incorporating manufacturing knowledge with chip design.This study aims to develop a two-phase non-dominated sorting particle swarm optimization （TNSPSO）method to maximize number of gross die and minimize the shot number by suggesting alternative chip features for IC designers. To evaluate the validity of proposed approach, two conventional heuristic algorithms, non-dominated sorting genetic algorithm II （NSGA-II） and multi-objective particle swarm optimization （MOPSO） were used to compare. The experiment results showed that the proposed method can not only find the solutions closer to the Pareto frontier but also the convergence and the diversity of the solutions are better.

並列關鍵字

chip size ； wafer exposure effectiveness ； particle swarm optimization ； Pareto optimal solution ； IC design

參考文獻

Chien, C.-F., Hsu, S.-C., Chen, C.-P.,, “An iterative cutting procedure for determining the optimal wafer exposure pattern,” IEEE Transactions on Semiconductor Manufacturing, vol. 12, no. 3, pp. 375-377, 1999.

Chien, C.-F., Hsu, S.-C., Deng, J.-F., “A cutting algorithm for optimizing the wafer exposure pattern,” IEEE Transactions on Semiconductor Manufacturing, vol. 14, no. 2, pp. 157-162, 2001.

Chien, C.-F., Hsu, C.-Y., Chang, K., “Overall Wafer Effectiveness (OWE): A novel industry standard for semiconductor ecosystem as a whole,” Computers & Industrial Engineering, vol. 65, no. 1, pp. 117-127, 2013.

Coello, C. A., Lechuga, M. S., “MOPSO: A proposal for multiple objective particle swarm optimization,” in Proceedings of the 2002 Congress on Evolutionary Computation, pp. 1051-1056, 2002.

Coello, C. A.,Pulido, G. T., “Handling multiple objectives with particle swarm optimization,” IEEE Transactions on Evolutionary Computation, vol. 8, no. 3, 2004.