一個適用於結合標準元件與智慧產權元件之穿孔可程式化的結構化客製晶片繞線器

A Router for Via Configurable Structured ASICs with Standard Cells and IPs

何瓊枝(Chiung-Chih Ho)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2013年)

https://doi.org/10.6838/YZU.2013.00314

摘要

數位積體電路（digital IC）隨著製程的進步，光罩的成本與設計的複雜度也愈來愈高。為了在成本與效能間取得平衡，結構化客製晶片（Structured ASIC）成為設計者的一個選擇。結構化客製晶片的存在正好彌補了半客製化積體電路設計（Cell-based/Standard cell ASIC）與現場可程式化邏輯閘陣列（FPGA）間的空白地帶。過去曾有一些學術研究提出針對結構化客製晶片的繞線方法，但都未提及是否考慮當一個結構化客製晶片同時含有標準元件（standard cell）及智慧產權元件（IP）的情況。本論文設計了一個適用於結合標準元件（standard cell）與智慧產權元件（IP）之穿孔可程式化的結構化客製晶片繞線器。此外，除了探討晶片繞線前的步驟如元件的擺置（placement）及電源規劃（power planning）等相關議題外，也會研究當我們搭配使用不同的全域繞線器（global router）時所造成的影響。實驗結果顯示，我們的繞線器在各種不同的繞線結構（routing fabric）下皆可快速且成功的完成繞線。

關鍵字

結構化客製晶片 ； 繞線器 ； 智慧產權元件

並列摘要

With the advances in integrated circuit(IC) technology, the costs of designing and manufacturing ICs increase dramatically. Structured ASIC was proposed for bridging the gap between standard cell ASIC and FPGA, and it’s a good choice for designer to balance the cost and performance. A few structured ASIC routers were proposed, however, none of them are able to handle a design containing IP blocks. In this thesis, we present a router which extends our previous work, Rover, for via configurable structured ASIC with standard cells and IPs. We also discuss some related issues such as placement and power planning issues related to router design. Moreover, we port two global routers, NTHU-route 2.0 and NCTU-GR, into our router. Experimental results show that our router can quickly and successfully route a via-configurable structured ASIC with standard cells and IPs.

並列關鍵字

structured ASIC ； router ； regular fabrics ； IP

參考文獻

[1] B. Zahiri, “Structured ASICs: opportunities and challenges,” ICCD, pp. 404-409, 2003.

[2] V.Kheterpal, A. J. Strojwas and L. Pilegg, “Routing Architecture Exploration for Regular Fabrics”, DAC, pp. 204-207, 2004.

[3] N. V. Shenoy, J. Kawa, and R. Camposano, “Design automation for mask programmable fabrics,” DAC, pp. 192-197, 2004.

[4] Y. Ran and M. Marek Sadowska, “An Integrated Design Flow for a Via-Configurable Gate Array,” ICCAD, pp. 582 – 589, 2004.

[5] L. C. Lai, H. H. Chang and R. B. Lin, “Rover: Routing on Via-Configurable Fabrics for Standard-Cell-Like Structured ASICs”, GLSVLSI, pp. 37-42, 2011.