本論文以臺積電所提供CMOS 0.18 μm製程實現適用於車載專用短距離通訊系統之射頻發前端射機設計與實現。此發射機為一次昇頻,運用於5.8 GHz頻帶平均輸出功率為10 dBm,增益約為23 dB,輸出三階截斷點為20 dBm,整體功耗為68mW。其中昇頻混頻器採類似Gilbert-cell架構作雙平衡操作,而主動濾波器電路採用共源極放大器加上退化電感與cascode兩種方式,以差動技術完成。最後一級為三模態功率放大器,4/π-DQPSK調變時操作在線性區作線性放大,同時加入線性器架構提高其線性度,而FSK、ASK調變時為非線性操作以提高其效率,最後加入被動之功率檢測器將功率訊號轉換成直流電壓訊號,此訊號回授給主控端可得知輸出訊號之大小。最後論文將依據量測結果討論電路設計未來改善方向。
This thesis presents an RF front-end transmitter design in TSMC CMOS 0.18 μm technology for dedicated-short-range-communications (DSRC) system applications. The transmitter utilizes one-step up-converter architecture to achieve an average output power of 10 dBm in 5.8GHz band, with total gain in 23 dB and 20 dBm in output third-order intercept point. The overall power consumption is about 68 mW. In the circuit designs, the up-convert mixer uses a double-balance operation similar to Gilbert-cell structure. The active band pass filter is in the common source amplifier, together with the use of both inductive source degeneration and cascode configuration, in a fully differential architecture. The last stage is a triple mode power amplifier (PA), where the PA works at the linear region as 4/π-DQPSK modulation signal applied, with an additional linearizer to improve the linearity, and the PA works at nonlinear region to enhance the efficiency as FSK and ASK modulation signal applied. A power detector is attached to the PA to detect the RF signal strength in dc voltage representation to acknowledge the host controller. Finally, this thesis will discuss the improvement directions in the future based on the current measured results.