一個使用雙供應電壓的結構化客製晶片之低功率設計方法

A Low Power Design Methodology for Structured ASIC using Dual Supply Voltages

林昆蔚(Kuen-Wey Lin)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2009年)

https://doi.org/10.6838/YZU.2009.00287

摘要

一個使用雙供應電壓的結構化客製晶片之低功率設計方法

關鍵字

雙供應電壓 ； 結構化客製晶片 ； 低功率 ； 設計方法

並列摘要

With rapid technological advances, manufacturing and design processes of cell-based design has become extremely complicated. Structured ASIC can potentially fill this gap [1]. Extensive research has proposed the design of basic cell in Structured ASIC for performance, area, and power issues [2][6]. If Structured ASIC is to become a viable alternative to cell-based design, it must deliver performance and energy efficiency which is competitive with cell-based design techniques. Supply voltage reduction is one of the most effective techniques in reducing power consumption of CMOS circuits. The total current to be delivered by the voltage supplies is significantly reduced in dual- or multiple- VDD circuits [3][7][9][10][14][15][22][23]. On-chip power distribution grids with multiple power supply voltages and multiple grounds are used for more flexible placement and routing[4][17][18]. In this thesis, we propose the design methodology of Structured ASIC using multiple supply voltage based on dual VDD power delivery model. We will describe issues such as VCLB of dual VDD delivery system, multiple supply voltage assignment algorithm, high speed level converter and flexible placement exploiting dual VDD delivery.

並列關鍵字

Dual Supply Voltages ； Structured ASIC ； Low Power ； Design Methodology

參考文獻

[1] Zahiri, B., "Structured ASICs: opportunities and challenges," in Proceedings of the 21st International Conference on Computer Design, 2003, pp.404-409 (ICCD’03)

[2] Ran, Y.; Marek-Sadowska, M., "Designing via-configurable logic blocks for regular fabric," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.14, no.1, pp.1-14, Jan. 2006 (TVLSI’06)

[3] Usami, K.; Igarashi, M.; Minami, F.; Ishikawa, T.; Kanzawa, M.; Ichida, M.; Nogami, K., "Automated low-power technique exploiting multiple supply voltages applied to a media processor," Solid-State Circuits, IEEE Journal of, vol.33, no.3, pp.463-472, Mar. 1998 (JSSC’98)

[5] Li, M.; Tung, H.; Lai, C.; and Lin, R., “Standard Cell Like Via-Configurable Logic Block for Structured ASICs,” in Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI, 2008 (ISVLSI’07)

[10] Jun Cheng Chi; Hung Hsie Lee; Sung Han Tsai; Mely Chen Chi, "Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.15, no.6, pp.637-648, June 2007 (TVLSI’07)