雙閘極電晶體之模型分析並應用於K頻段變壓器低雜訊放大器之設計

Analysis and design of Dual-Gate N-MOSFETs model for K-band transformer-based LNA applications

蘇思豪(Sy-Haur Su)

指導教授 ： 徐碩鴻

國立清華大學/電機資訊學院/電子工程研究所/碩士(2009年)

https://doi.org/10.6843/NTHU.2009.00687

摘要

With the growth of the IT industry, the technologies of communication arouse more and more attention in these years. Recently, the demand for high data rate makes the desired operation frequency of RFICs moving toward higher bands. Among the applications, K-band (18 - 26.5 GHz) is of great interest, which can be used for short-range and high data-rate wireless communication systems eg: UWB (Ultra wideband) and LMDS (local multipoint distribution systems).
In the first part of this dissertation, a cascode dual-gate CMOS model is presented. The proposed passive network represents the physical-based parasitic components of the device. The extrinsic elements of substrate networks, and distributed resistances and inductances of the gate, source and drain terminals are extracted from the measured S- parameters. Good agreement from 100MHz to 50GHz has been obtained between simulation and measurement of small-signal S-parameters.
In this work, three low noise amplifiers (LNAs) were realized based on the transformer feedback configuration for K-Band applications. All circuits used the on-chip transformer as the input matching network for better noise and power matching. All of them were implemented by a standard 0.18-um CMOS technology. Among them, the cascode design achieved a noise figure of 4.3 dB under a power gain of 15.3 dB for ISM band applications. The wideband amplifier design achieved a noise figure of 5.2-6.2 dB under a power gain of 10.3 dB at 21-27 GHz. The common source design used two kinds of transformer feedback topologies for the differential amplifier which achieved a noise figure of 4.8 dB under the power gain of 9.2 dB at 27 GHz.

關鍵字

雙閘極

並列摘要

無資料

並列關鍵字

daul gate

參考文獻

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