Jointly Designed Architecture-Aware LDPC Convolutional Codes and Its Memory-based Parallel Shuffled Decoder Architecture

聯合設計架構取向低密度奇偶檢查迴旋碼並且以記憶體存取之平行混合運算解碼器架構

甘禮昇(Li-Shegn Kan)

指導教授 ： 翁詠祿

國立清華大學/電機資訊學院/電機工程學系/碩士(2011年)

https://doi.org/10.6843/NTHU.2011.00060

摘要

In this thesis, we jointly design architecture-aware (AA) low-density parity-check convolutional codes (LDPC-CCs) and the associated memory-based parallel decoder architecture based on shuffled message-passing decoding (MPD). We propose a method of constructing AA-LDPC-CCs that can facilitate the design of a memory-based shuffled decoder using parallelization in both iteration and node dimensions. The codes are constructed such that hazards in memory access can be avoided in this decoder. Through the use of shuffled MPD, the number of base processors and, hence, the decoder area is significantly reduced, since a fewer number of iterations is required to achieve a desired error performance. The inherent regularity in the AA-LDPC-CCs is utilized to reduce the area of each base processor in the decoder. In the memory-based decoder, the difficulty of exchanging information between iterations (processors) is overcome by simple permutation networks. To demonstrate the feasibility of the proposed techniques, we constructed a time-varying (479, 3, 6) AA-LDPC-CC and implemented its associated shuffled decoder using a 90-nm CMOS process. This decoder comprises 11 processors, occupies an area of 5.36 mm2, and achieves an information throughput of 1.025 Gbps at a clock frequency of 256.4 MHz based on post-layout results.

關鍵字

low density parity check convolutional codes ； shuffled ； VLSI

並列摘要

在這篇論文中，我們設計了架構取向的(architecture-aware以下簡
稱AA)低密度奇偶檢查迴旋碼(LDPC-CC)並且提出以記憶體儲存資訊之
Shuffled MPD平行運算解碼器架構。

我們提出了一個建構AA-LDPC-CC的方法，使能夠以記憶體存取且可同時平行處理
於疊代解碼與多節點運算兩種維度的Shuffled解碼器。此碼被建構
於避免解碼器上記憶體存取上之資料碰撞，且能解決使用管線架構造成
之效能損失。

LDPC-CC解碼器是由基本運算單元(processor)串接而形成整個解碼運算，
而且每個processor代表每一次疊代(iteration)解碼，因此LDPC-CC解碼器之
疊代解碼次數取決於processor之數量。
相較於傳統LDPC-CC使用Two-Phase MPD解碼，在此篇論文我們選用Shuffled MPD解碼，
因為Shuffled MPD只需要較少的疊代解碼次數便能達到相同的錯誤效能。
藉由減少processor之數量，此解碼器面積會有效的降低。
且此解碼器由於使用記憶體存取，相較於傳統LDPC-CC使用位移暫存器，
使用記憶體存取在交換資訊於各個processor之間有一定的困難度，
但在此我們利用簡單的旋轉繞線克服。

為了驗證這提出的解碼器，我們建構了一個隨
時間時變的(479,3,6)AA-LDPC-CC且使用90-nm CMOS製成
來實現這Shuffled解碼器。在post-layout下的結果，此解碼器結
合了11個processor共占了5.36mm2，且在頻率為256.4MHz之下
能達到資訊吞吐量1.025 Gbps。

參考文獻

[1] R. G. Gallager, “Low density parity check codes,” IRE Trans. Inform.

[2] D. J. C. MacKay, “Good error correcting codes based on very sparse

capacity-approaching irregular low-density parity-check codes,” IEEE

[4] T. Mohsenin, D. Truong, and B. Baas, “A low-complexity messagepassing

algorithm for reduced routing congestion in LDPC decoders,”