透過您的圖書館登入
IP:3.136.85.225
  • 學位論文

嵌入式可雙向線性調適之非揮發性類比記憶體

An embedded, analogue nonvolatile memory with bi-directionally linear adaptability

指導教授 : 陳新
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


隨著時代的演進,現代社會在生醫領域的研究日趨重視,而長時間在人體表皮層下的生醫探測人體狀況的晶片也漸漸被需要,而類比記憶體常出現在生醫晶片中,用來記錄長時間晶片學習記錄人體情況的結果. 此研究的主要目標是在標準0.35微米互補型金氧半製程下,設計出聰明可動態雙向線性調適的高解析非揮發性類比記憶體,而設計方向則是側重雙向調適,線性,高解析度,操作簡易,快速完成寫入,並觀測其在長時間常態溫度下記憶體儲存的有效時間常度. 研究中從以HSPICE建構能夠模擬出熱電子熱電洞特性的合理模型,進而模擬類比記憶體的電路特性,以此條件下模擬設計出電壓型可雙向線性調適,並具有超過8位元解析度的類比記憶體.再經由下線後得到量測晶片的量測數據與HSPICE電路模擬結果做比較,檢測晶片之特性是否符合HSPICE模擬的結果. 當記憶體單元的特性量測結果與模擬情況符合後,就接續著模擬並下線記憶體陣列晶片,設計以及量測針對此電壓型雙向線性調適非揮發性記憶體的陣列,用以驗證個別記憶體單元間寫入是否會彼此干擾的情況,並在此晶片量測寫入速度加快的結果是否符合預期結果.最後則是做資料保存(data-retention)的量測,記憶體儲存值以儲存三個月以上為目標時間,藉由資料保存相關理論以實驗數據求得長時間的記憶體儲存值情況.並且改善加快寫入速度.當資料保存量測與理論驗證後,接著研究方向朝陣列架構的電路模擬與下線. 最後,隨著研究過程的推進,各式各樣的問題以及現象隨之浮現,在本研究的最後部分會提出並給予一些想法與解決情形來討論總結.

並列摘要


Floating-gate devices have been widely used in many commercial products as memory cells. In this paper, a bidirectionally-programmable non-volatile analog storage cell has eight effective resolutions to write or erase information. The memory cell, which stores the analog information in the MOS transistor floating-gate device, is written and erased by means of hot-electron injection and hot-hole injection. The memory circuit can write or erase the target value to the floating-gate devices and it is achieved by a simple, on-chip comparator. By using a comparator, the circuit controls the programming mechanisms automatically that the storage analog information can be programmed to the target value precisely under negative feedback. Errors due to the effects of device mismatches or trapping can be eliminated by the feedback control. By modeling the programming mechanisms, the proposed analog memory circuit is designed and can be used in analog neural networks. The proposed analog memory circuit has the storing voltage range from 0.6V to 2.2V and the error voltage less than 5mV. In this experiment, data-retention should be tested after the design of the memory cell was finished. the data-retention test results can be used to estimate the storage time in which the memory cell holds the storage information. In the end, a memory-cell array is designed by using floating-gate technique to store analog information.

並列關鍵字

memory nonvolatile linear embedded

參考文獻


[1]褚明儒,「擴散網路」晶片系統神經元的超大型積體電路設計,碩士論文,國立清華大學,2005.
[7]黃正達,高解析度非揮發性類比記憶體研究發展,碩士論文,國立清華大學,2007.
[2]盧峙丞,連續值局限型波茲曼模型積體電路系統之模組化及程式化設計,博士論文,國立清華大
[4]K. Lee and Y. King, “New single-poly EEPROM with cell size down to 8F2 for high density embedded
[5]K. Rahimi, C. Diorio, C. Hernandez, and M. Brockhausen, “A simulation model for floating-gate MOS

被引用紀錄


潘欣婷(2013)。嵌入式非揮發性類比記憶體陣列之寫入速度改善及於生物分子感測之應用〔碩士論文,國立清華大學〕。華藝線上圖書館。https://doi.org/10.6843/NTHU.2013.00240

延伸閱讀