內建差動讀取的非揮發性記憶體元件研究

The Study of CMOS Logic Based Nonvolatile Memory Cells with Built-in Differential Read Operation

李德量(Lee, Te Liang)

指導教授 ： 林崇榮 ； 金雅琴

國立清華大學/電機資訊學院/電子工程研究所/博士(2013年)

摘要

本論文提出三種可應用於嵌入式系統單晶片的新式差動讀取之非揮發性記憶體元件。所提出的新式差動讀取之非揮發性記憶體元件以完全邏輯製程相容或既有的非揮發性記憶體技術製作，故可維持與現行業界非揮發性記憶體解決方案的可行性及效能。同時，藉由其差動讀取的雙倍window以提昇浮動閘極非揮發性記憶體的資料保存能力。另外，除了可相容於邏輯製程之非揮發性記憶體元件，可相容於邏輯製程之高壓元件也被提出，進而達成完全邏輯製程相容之嵌入式系統的非揮發性記憶體模組。
首先，本論文討論兩種邏輯製程相容的新型差動式多次性可編程非揮發性記憶體。接著，為實現完全邏輯製程相容的嵌入式系統之非揮發性記憶體模組，本文也討論一個可完全相容於邏輯製程之高壓接點閘極金氧半場效電晶體。
此外，我們也提出一種新型差動式同時具有自我修復能力的分離式閘極快閃記憶體。由於，分離式閘極快閃記憶體的快速編程、抹除的能力已被驗證，利用差動式讀取及其自我修復能力更提昇其資料保存能力，使之可運用於高可靠性需求的產品。
總結，本文提出數種可基於原有非揮發性記憶體架構及製程，提昇非揮發性記憶體資料保存能力的解決方案。這些解決方案可保留已驗證非揮發性記憶體元件之優勢，不需額外的製程調整及控制，便可運用於更高可靠性需求的產品應用之上。

關鍵字

非揮發性記憶體 ； 差動讀取 ； 自我修復能力 ； 邏輯製程相容 ； 嵌入式系統單晶片

並列摘要

This dissertation proposes three types of new novel differential nonvolatile memory (NVM) cells for advanced embedded system on a chip (SOC) applications. The novel NVM cells with differential read function were fabricated by fully complementary metal–oxide–semiconductor (CMOS) logic compatible processes or existing NVM technologies, so that their feasibility and performance are comparable to the current industrial NVM solutions. Moreover, the floating gate (FG) data retention performance can be enhanced by the differential read operation, which has a double read window. Further, in addition to the logic-compatible NVM cells, a logic-compatible high voltage device which can realize a fully logic-compatible NVM module for embedded systems was also proposed.
First, two fully logic-compatible multiple-time programmable (MTP) floating gate NVM cells with differential read operations are proposed. Then, in order to realize a fully logic-compatible NVM module for embedded systems, a high voltage contact gate metal–oxide–semiconductor field-effect transistor (MOSFET) with fully logic-compatible process was also proposed.
In addition, a new high-density differential split-gate flash memory cell with self-recovery function is proposed. Since the cell process and tip erase structure are totally inherited from the proven split-gate flash technology, the highly efficient program and erase performances are retained in the new cell. However, data retention and endurance capability are much improved by the new built-in self-recovery function with differential read operation.
In summary, several data retention performance enhancement solutions based on existing proven NVM cell structures are discussed in this dissertation. These solutions, which maintain the advantages of original NVM cells, can be directly used for high reliability requirement products without any special process tuning or control.

並列關鍵字

Nonvolatile Memory ； Differential Read ； Self-recovery ； Logic Process Compatible ； Embedded SOC System

參考文獻

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