低延遲場效可程式化邏輯閘陣列加速之高頻交易系統

A Low Latency FPGA-Accelerated High-Frequency Trading System

陳泓安(Hung-An Chen)

指導教授 ： 馬席彬

國立清華大學/電機資訊學院/電機工程學系所/碩士(2021年)

摘要

大多數的交易系統使用網卡以及軟體作為基底進行封包處理與交易決策，然而，在網卡與中央處理器傳輸資料的過程中，造成快取未中、中斷網路堆棧等無法預期的延遲，導致系統延遲較長。因此，為了在快速變動的市場中迅速因應變化以從中獲取利潤，在本篇論文中設計出一個可應用於百億位元乙太網路的高頻交易系統，透過現場可程式化邏輯閘陣列進行硬體加速，進而減少系統延遲並使高頻交易者的獲利效率提升。
在此系統中，為了克服在卸載TCP/IP以及UDP/IP封包時，傳統網卡使用 PCIe與中央處理器進行資料傳輸所造成的延遲，系統採用延遲約25奈秒、運作於312.5兆赫時脈且資料寬度為32位元之百億位元乙太網路實體收發器收取來自台灣期貨交易所之行情與交易封包。由於封包欄位固定，使用計數器以及尋找表設計客製化網路分層，對封包進行解析得到負載，並且根據台灣期貨市場之金融訊息規範進行解碼，得到相關行情訊息以更新本地端之客製化商品委託簿。根據委託簿所更新之五檔價量，系統採用簡易套利策略對此進行條件判斷，確認下單與否。另外，為了增加彈性與使用上的便利性，可依據不同交易環境設定不同的參數進行連線或斷線，亦可手動制定交易參數執行交易委託。
本篇論文交易系統之硬體與功能測試，使用元大期貨所提供的台灣期貨交易環境驗證連線、策略下單與手動下單功能之正確性，並且使用iPerf與Viva-do估算現場可程式化邏輯閘收發器以及系統內部之延遲。從現場可程式化邏輯閘之接收器收到封包至發送器發出封包延遲約480奈秒，系統內部行情封包解析至委託封包觸發延遲約433奈秒，相比舊有系統延遲減少約20%，而相比其他文獻以軟體方法實現之交易系統延遲，效能提升大約百倍。

關鍵字

高頻交易 ； 硬體加速 ； 期貨 ； 場效可程式化邏輯閘陣列 ； 交易系統

並列摘要

Most trading systems use network interface controllers (NICs) and software as the base for packet processing and decision making of trading. However, it will cause unpredictable latency resulted from cache miss and interrupt-driven network stack in the process of data transfer between the NIC and the CPU, making the system latency longer. Therefore, in order to quickly respond to changes in a rapidly changing financial market and obtain profits from it, a high-frequency trading system for 10 gigabit Ethernet is designed in the thesis. By implementing hardware acceleration for trading process on FPGA, the latency of trading system can be reduced and the profitability and efficiency of the high-frequency traders can be increased.
In the system, in order to overcome the latency resulted from the data transfers for offloading TCP/IP and UDP/IP packets between traditional network interface controller (NIC) and host central processing unit (CPU), the system adopts a 10 gigabit Ethernet physical transceiver which runs at a clock frequency of 312.5 MHz with a low latency of 25 nanoseconds and a data width of 32 bits to transfer the market feeds and order packets from and to Taiwan Futures Exchange. Because of the fixed fields in the packets, the customized network stack is designed based on counters and lookup tables to analyze the packets, get the payloads and decode the payloads to obtain the financial messages according to the specification of Taiwan futures market. Afterwards, the local customized order book of specific commodities can be updated and the trading strategy for arbitrage determines whether to place an order according to the best five levels of sizes and prices in the updated order book. In addition, the system allows traders to set different trading environment to connect or disconnect, and manually set up trading parameters to execute custom trading orders.
The hardware test and functional verification of the trading system in the thesis use Taiwan futures trading environment provided by Yuanta Futures to verify the correctness of connection, strategic and manual ordering functions, and I use iPerf and Vivado to estimate the latency of transceiver on FPGA and inside the system. The latency from receiving the packet to the transceiver on FPGA is approximately 480 nanoseconds, and the latency from the internal market packet analysis to the ordering packet triggered is approximately 433 nanoseconds. Compared with the existing architecture, the latency is reduced about 20%. Besides, compared with the latency of the trading system implemented by software method in other literature, the performance is improved by about a hundred times.

並列關鍵字

High-Frequency Trading ； Hardware Acceleration ； Futures ； FPGA ； Trading System

參考文獻

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