先進微電子封裝技術之設計、結構可靠度分析與電遷移效應評估

Design, Structural Reliability Assessment, and Electromigration Evaluation for the Advanced Microelectronic Packages

游明志(Ming-Chih Yew)

指導教授 ： 江國寧

國立清華大學/工學院/動力機械工程學系/博士(2009年)

摘要

本研究針對先進晶圓級封裝技術(wafer level package, WLP)之改良與設計概念進行討論，焊錫接點位置應力釋放(solder joint stress release)與電子元件訊號扇出(IC signal fan-out)能力為選定之主要設計目標；研究中提出適用於新型電子封裝結構之相關基本理論與可靠度分析技術，並使用發展之電遷移(electromigration)試驗方法尋找新型態晶片封裝技術對其內埋電子元件電遷移現象可能造成之影響。

參考規劃之設計目標，分別使用兩種先進封裝技術作為測試載具並輔助研究進行；其中在具有錫球保護特性之晶圓級封裝(solder joint protection wafer level package, SJP-WLP)中，使用一位於介電層與晶片間之剝離界面達到釋放焊錫接點處累積應力之目的；另一方面，嵌板式封裝(panel base package, PBP)其在選定之嵌板材料上方完成封裝程序，可同時擁有釋放焊錫接點位置應力與扇出電子元件訊號兩項特性。在新型封裝技術中可能使用異於傳統之封裝材料與結構設計，其發生之熱-機械力學行為亦可能不同，藉由本研究中提出之相關分析方法，可針對包括焊錫接點、封裝結構內金屬導線、以及半導體元件中後段製程導線(back end of line, BEOL)進行可靠度評估。針對金屬導線疲勞模型中之疲勞係數求取，可利用有限元素分析方法搭配封裝體可靠度實驗獲得，達到預估金屬導線於溫度循環負載下疲勞壽命之目的；另，利用四點彎矩設備(four-point bending apparatus)可對電遷移實驗中之測試線路直接施加機械應力，研究中藉由此一方式討論先進封裝設計對其內埋元件中後段製程導線電遷移破壞行為可能產生之影響；實驗結果顯示外加機械應力分別僅對鋁/矽/銅與銅金屬導線對應之平均壽命(MTTF)造成有限之影響，然而該數值變化可能導致在布雷克方程式(Black’s equation)中參數求取過程發生誤差，藉由控制金屬導線內部殘餘應力使其位於該結構之抗拉降伏強度(tensile yielding strength)與抗壓降伏強度(compressive yielding strength)之中間值，預期將可提高金屬導線之抗電遷移能力並降低機械應力對使用布雷克方程式時所可能產生之影響；另，具有較強機械強度之金屬導線可降低應力導致孔洞遷移(stress-induced voiding)之發生，亦為建議之導線設計方向。

本研究中提出適用於先進電子封裝技術之分析流程，藉由適當測試載具之驗證，其可達到輔助先進晶圓級封裝設計、結構可靠度分析，以及電遷移效應評估之目的；因此，其內容可作為電子封裝領域研究人員發展新型態封裝技術時之重要參考。

關鍵字

晶圓級封裝 ； 有限元素分析 ； 疲勞壽命預估 ； 電遷移 ； 四點彎矩

並列摘要

In this research, the improvements and design concepts of advanced wafer level package (WLP) are studied. Two major targets, the solder joint stress release and the integrated circuit (IC) signal fan-out, are especially focused. Due to the demands of the suitable analytic methods applied on the reliability assessment of advanced microelectronic packages, the related fundamental theories and testing approaches are proposed. In addition, the electromigration performance of the embedded IC related to the applied new packaging designs is examined by the presented experiment.

Based on the objective design concepts, two types of novel packaging structures are fabricated to assist the investigation. One idea, the solder joint protection WLP (SJP-WLP), is developed by applying a delaminating layer interposed between the lowest insulation layer and the top surface of the silicon chip. Besides, the panel base package (PBP), which is fabricated on a selected panel material, is also designed to achieve both the capabilities of solder joint stress release and IC signal fan-out. Because of the applied new packaging materials and structures in advanced microelectronic packages, the thermal-mechanical behaviors are different from the conventional cases. By using the established analytic methods, the reliability assessment of solder joints, redistribution lines, and the back end of line (BEOL) of IC devices are studied. The fatigue parameters in prediction model are determined through the FE analysis and the related experiment. Therefore, the lifetime of metal traces under temperature cycling test can be predicted through the FE analysis together with the fatigue model. Besides, the four-point bending apparatus is used to directly impose mechanical loading on testing metal wires, and the influence from packaging designs on electromigration damage is studied. From the results, the applied mechanical stress has a small but finite effect on the MTTF of the Al/Si/Cu and Cu metal lines. However, this variation may lead to an error estimation when calculating the unknowns in the Black's equation. To improve the electromigration reliability and reduce the effects of the mechanical stress on the application of the Black's equation, the residual stress is suggested to be controlled to the mid-value between the compressive and the tensile yielding strength of the metal lines. In addition, metal lines with larger yielding strength are also favorable due to their better resistance of stress-induced voiding (SIV).

The analytic procedures which are suitable for future microelectronic packages are proposed in this research. By means of the validation on the testing specimens, they can be applied well on the design, structural reliability assessment, and electromigration evaluation of the advanced WLP. To develop the advanced microelectronic packages, this research could be quoted as an important reference by the packaging engineers.

並列關鍵字

Wafer level package ； Finite element analysis ； Fatigue life prediction ； Electromigration ； Four-point bending

參考文獻

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