在後矽調整電壓以提升效能良率並考慮功率消耗之演算法

當半導體的製程進入奈米的等級後，製程變異的影響（process variation）讓晶片在量產時，晶片的良率持續地惡化。在『1』，作者提出了一套以列電壓調整的方法允許使用者微調已製造晶片的供給電壓（supply voltage）。在此論文中提出一套可以減少製成變異影響的方法，當晶片製作完成且無法通過測試時可以藉由微調供給電壓的方式來修正晶片，以提昇良率。但是並未調提到如何有效率的決定每一個供給電壓的調整方式，這個調整方式必須使得晶片能運作在合格的速度下和增加最小的功率消耗。在我們的論文中，我們嘗試的開發一套電壓調控的機制，用來決定如何調整電壓已校調發生錯誤的晶片。在可調整電路中，供給電壓（VDD）與接地電壓（GND）皆可以相較於正常電壓調整+/-0.2伏，也就是每一個電壓都有三種值。當一個晶片中有N個可調整的供給電壓，這樣一共就有3N種解的可能。然而，大部分的解都不是合適的解或是不能修正發生錯誤的晶片。因此，我們提出了一個可以決定電壓的方法，這方法將可找出符合規格的解。我們再依照這解去調整實際晶片的電壓。在實驗方面，我們的電路採用180奈米製程技術。我們試著修正錯誤的晶片，這些錯誤的晶片以系統性的方式加入不同的延遲使得晶片的時脈超出預期的規格。在s38584中我們可以修正超過25.49％的時脈延遲。而我們的方法在各種電路與加入不同的時脈延遲下與正常電壓下的功率消耗比較大約分佈在-4.56％到43.07％間。一般來說，當晶片增加的延遲越少增加的功率消耗也越少。沒有這套方法我們只能一起調整整個晶片的電壓，例如，將整個晶片的VDD都調整到2.0v和GND都調整到-0.2v，在180奈米製程下，消耗的功率會增加49％。我們提出的方法不僅可以修正有效的修正錯誤的晶片也減少功率的消耗

關鍵字

可調式電路；提昇效能良率

並列摘要

As the CMOS technology comes forward to nanometer scale, process variation increasingly deteriorates the yield of mass production. In [1], the authors proposed a row-based tunable design methodology which allows users to fine-tune the supply voltages of manufactured chips. The method presented in that thesis is able to mitigate the effect of process variation by fine-tuning the supply voltages for fabricated chips that originally fail the IC test. Yet, no effective algorithm has been proposed to determine how to adjust the supply voltages which would gain the sufficient chip speed and increase minimum power consumption. In this thesis we attempt to develop a voltage assignment algorithm for the decision of how to adjust the supply voltages for regulating failed chips. In the tunable circuits, the supply voltage (VDD), ground voltage (GND) and body bias can be adjusted up to +/- 0.2 Volt over the nominal voltage respectively, e.g. the voltage level of each cell could have three possibilities. If a chip has N tunable supply voltages, there are N3 solutions for this problem. Nevertheless, most of the solutions are not feasible or unable to regulate the failed chips. Hence, a voltage assignment algorithm is proposed to look for a solution that can satisfy the expected specification. We will follow the solution to adjust chip voltage. In the experiments, we have applied our method on the circuits under 180nm process node. We try to fix failed chips which are injected different amount of extra delay in a systematic way. In s38584, we can fix failed chips with up to 25.49% excessive delay over nominal timing spec. The range of dynamic power overhead is as low as -4.56%-43.07% compared to a typical voltage assignment case. Generally, chips with less excessive delay could result in less dynamic power overhead. Without this method, we can only conservatively apply the assignment best to timing, i.e. tune all VDD to 2V and GND to -0.2V for the 180nm process node, while this assignment would lead to more than 49% of the dynamic power overhead. The proposed algorithm can not only effectively fix failed chip in timing but reduce the power consumption.

並列關鍵字

Cell-based Tunable Circuit ； Increasing Performance Yield

參考文獻

[2] M. Choi and L. Milor, “Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1350–1367, 2006.

[3] M. Eisele, J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf, “The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 4, pp. 360–368, 1997.

[4] K. Bowman, S. Duvall, and J. Meindl, “Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration,” IEEE Journal of Solid-State Circuits, vol. 37, no. 2, pp. 183–190, 2002.

[5] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter variations and impact on circuits and microarchitecture,” ACM/IEEE Design Automation Conference, pp. 338–342, 2003.

[6] K. Usami and M. Horowitz, “Clustered voltage scaling technique for low-power design,” Proceedings of the 1995 international symposium on Low power design, pp. 3–8, 1995.

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在後矽調整電壓以提升效能良率並考慮功率消耗之演算法

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