奈米級互補金屬氧化半導體製程下之強健的靜態隨機存取記憶體設計技術

Resilient SRAM Design Techniques for Nanometer CMOS Technology

賴亞群(Ya-Chun Lai)

指導教授 ： 黃錫瑜

國立清華大學/電機資訊學院/電機工程學系/博士(2009年)

摘要

在先進的奈米級互補金屬氧化半導體(CMOS)製程下之內嵌式靜態隨機存取記憶體正遭遇良率危機，此乃是由於增加的製程變異導致惡化的記憶胞之靜態電性參數所造成，如靜態雜訊間隙及寫入間隙的下降。另外，顯著的漏電流導致更多靜態功率消耗和惡化訊號完整性，例如因過大位元線漏電流所造成之減少的驅動電流與漏電流的比值可能導致感測失敗，即不正確的讀取動作。近年來，許多電路設計技術已被提出用來增加記憶胞之操作間隙以便減少讀取和寫入失敗。然而，用來對付感測失敗之相關電路設計技術仍然不足，因此，我們發展了一些技術以處理感測失敗。X校正(X-calibration)意欲解決位元線漏電流問題，內建自我測試電路協助之時序追蹤提供強健之時序控制以便減少因感測放大器所造成之感測失敗。除此之外，自動電源關閉感測放大器避免了感測失敗並抑制傳統電流鏡感測放大器過度的靜態功率消耗，自我電壓調整不只可以自動地調整工作電壓至最低值，也能夠容忍溫度的變異。
從製作的晶片之量測結果顯示採用X校正之記憶體電路能夠對抗達到320μA之位元線漏電流，為未採用X校正之傳統記憶體電路的4.18倍。另一批製作的晶片之量測結果也證明內建自我測試電路協助之時序追蹤可以保證記憶體電路在一些外加變異因素的情況下運作之正確性。此外，使用自動電源關閉感測放大器的64Kb靜態隨機存取記憶體設計之模擬結果顯示比傳統電流鏡感測放大器節省28%到87%之功率消耗是可達到的。模擬結果也顯示具有速度間隙之自我電壓調整可以使64Kb記憶體電路容忍溫度變化達125℃。再者，量測結果確認使用強健的自我電壓調整方案之8Kb記憶體電路操作在150MHz下可以達到40%之功率節省。因此，合併我們的方法和前人所提之讀寫協助技術可以提供強健之靜態隨機存取記憶體以對抗製程、電壓及溫度之變異，進而改善靜態隨機存取記憶體之良率。

關鍵字

互補金屬氧化半導體 ； 靜態隨機存取記憶體 ； 漏電流 ； 製程變異 ； 感測放大器

並列摘要

Embedded static random access memory (SRAM) in advanced nanometer complementary metal-oxide-semiconductor (CMOS) technology for microprocessor, application-specific integrated circuit (ASIC), and system-on-chip (SoC) has been encountering yield crisis due to increased die-to-die and within-die threshold voltage (Vt) variations, which may deteriorate DC electrical parameters such as static noise margin (SNM) and write margin. Moreover, prominent leakage currents incur more static power consumption and degrade signal integrity. For example, decreased on-current to off-current ratio owing to excessive bit-line leakage may result in sensing failure, i.e., incorrect read operation. Recently, numerous circuit design techniques have been proposed to expand operating margin of bit cells so as to diminish read and write failures. However, circuit design techniques to cope with sensing failure are still insufficient. Therefore, we developed some techniques to deal with sensing failure. X-calibration scheme aims at addressing the bit-line leakage problem. BIST-assisted timing-tracking (BATT) scheme provides robust timing control to alleviate sensing failure caused by latch-type sense amplifiers. Automatic-power-down (APD) sense amplifier avoids sensing failure and suppresses extravagant static power consumption for conventional current-mirror sense amplifiers. Furthermore, the on-chip self-VDD-tuning scheme not only automatically tunes the supply voltage of an SRAM macro to the minimum value but also tolerates temperature variation.
Measurement results from fabricated chips demonstrate that the SRAM macro adopting X-calibration scheme can cope with up to 320μA bit-line leakage (4.18 times larger than the baseline SRAM macro) and that BATT scheme can warrant correct functionality of the SRAM design under some injected variations. Additionally, simulation results of a 64Kb SRAM design using the APD sense amplifier in a 22-nm predictive technology model (PTM) show that power reduction of 28%-87% over the traditional current-mirror sense amplifier is achievable. Simulation results in a 0.18-μm CMOS process show that a 64Kb SRAM macro employing the self-VDD-tuning scheme with speed margining can tolerate temperature variation up to 125℃. Measurement results from a test chip in a 0.18-μm CMOS process confirm that an 8Kb SRAM macro can achieve 40% power reduction at 150MHz by means of the resilient self-VDD-tuning scheme. Consequently, incorporating our techniques with the previously reported read/write assist techniques can provide a robust SRAM design against process, voltage, and temperature (PVT) variations, thus improving SRAM yield.

並列關鍵字

CMOS ； SRAM ； Leakage ； Process Variation ； Sense Amplifier

參考文獻

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