新穎梯形閘極氧化層反熔絲記憶元件應用於奈米製程技術

Novel Anti-Fuse with Step Gox Structure for Nano CMOS Logic Technology Application

吳泰億(Tai-Yi Wu)

指導教授 ： 金雅琴 ； 林崇榮

國立清華大學/電機資訊學院/電子工程研究所/碩士(2009年)

摘要

本篇論文提出一新穎以梯形閘極氧化層結構的反熔絲記憶元件(Step Gate Oxide Anti-Fuse, SGAF)，此記憶元件可內嵌於一般標準邏輯製程製作之晶片。利用光罩定義在同一閘極上形成厚薄氧化層而成梯形狀，並使用硬崩潰作為單次寫入型之機制，利用淺溝渠(Shallow Trench Isolation)可以避免未寫入記憶元受到貫穿電壓影響，隔離元件之間漏電流干擾。藉特殊元件佈局技巧及薄氧化層比例設計，可以增大電場效應，提升寫入資料速度。SGAF 記憶元件在高電壓寫入時低於4V，可避免大部份非揮發性記憶元件使用的高電壓，所造成的高功率損耗的缺失。元件陣列則採用NOR 型式陣列，並加入字元線選擇電晶體(select transistor)以降低超薄閘極漏電流干擾寫入及讀取情況，提高記憶元件可靠度。 此新穎之梯形閘極反熔絲SGAF 記憶元件驗證於90nm 和65nm 標準邏輯製程，經晶片量測結果顯示，1Kbits 陣列之記憶元件電流分佈，提供足夠的讀取電流差距，達成資料的存取。

關鍵字

梯形閘極反熔絲記憶元件 ； 單次型寫入 ； 非揮發性記憶體 ； 時間相依性介電氧化層崩潰分析模型 ； 熱化學崩潰模型 ； 陽極電洞注入模型 ； 氫滲透模型

並列摘要

In this study, a novel logic One-Time-Programmable (OTP) cell using Step Gate Oxide of Anti-Fuse (SGAF) with fast programming was demonstrated by nano-meter CMOS logic processes for advance logic NVM’s applications. The silicon data has proven that this cell can be adapted in both 90nm & 65nm technology nodes. The SGAF cell features complete compatibility to logic process without any
additional change in process or mask layers. Gate oxide rupture is used as programming mechanism for the SGAF memory cell. The unique design in this cell is creating a oxide thickness difference in this step gate oxide formation. This cell can be programmed under 4V within 10us, while this low programming voltage can greatly
reduce the power consumption as well as complexity in the peripheral circuits.
As the breakdown of gate oxide is used as the programming method in SGAF array memory cell, this device is expected to scale better in advance technologies.

並列關鍵字

Step Gate Oxide Anti-Fuse, SGAF ； One-Time-Programmable ； Non-Volatile-Memories ； TDDB model ； Thermo-chemical model ； Anode Hole Injection Model ； Hydrogen release model

參考文獻

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