應變工程在奈米尺寸CMOS元件製程之研究

Study of Strain Engineering for Nano-scale CMOS devices process

蔡宏聖(Hung-Sheng Tsai)

指導教授 ： 張書通

中原大學/工學院/電子工程研究所/碩士(2005年)

https://doi.org/10.6840/cycu200500201

摘要

中文摘要
本論文針對局部應變矽與非局部應變矽兩方面來研究。在局部應變矽方面，使用FLOOPS-ISE™和DESSIS-ISE™模擬所提到元件結構中之製程與電性，其中英特爾90奈米應變矽技術利用有應變的氮化矽層來增強NMOS 的效能。新加坡大學在2004 IEDM發表在源極/汲極區使用矽碳(SiC)增進50奈米場效N型電晶體特性。對於PMOS而言，英特爾在源/汲極區域相對應的兩端挖出稱為”壕溝(trenches)”的結構﹐然後填入具有較大晶格常數的矽鍺合金(SiGe)。所填入的矽鍺合金則會從兩側壓縮其間的矽通道﹐使得其電洞遷移率增加，且在最新的產品將會使用此技術量產，可見其重要性。在非局部應變矽方面，針對矽鍺異質結構場效電晶體與矽碳異質結構場效電晶體，使用ANSYSTM軟體由材料間之熱膨脹係數不匹配所造成的應變來模擬晶格常數不匹配。所模擬的結構為矽/矽鍺/矽與矽/矽碳/矽之平臺。
我們針對元件結構與合金之百分比來模擬製程所產生應變並分析元件上應變的分佈，討論其影響再將元件作簡單的電性分析。其研究結果與參考文獻相近，證明其方法可行，透過模擬後元件的應力分佈，進而推測電子或電洞載子遷移率，有利於控制元件讓PMOS與NMOS整合來提昇效能。

關鍵字

應變 ； 互補場效電晶體 ； 應力

並列摘要

Abstract
This paper reports the local process stress and the global process stress for CMOS devices. Both process and device simulations for the local process stress are simulated by FLOOPS-ISE™ and DESSIS-ISE™. The simulated process is similar to the 90 nm technology with a 50 nm gate length presented by Intel and NSU(National University of Singapore) in which a compressive/tensile strain is introduced in the PMOS/NMOS channel using embedded SiGe/SiC pockets in the source and drain areas. Tensile stain in the channel of NMOS induced by a high tensile strain silicon nitride capping layer is also studied.
For CMOS devices which the global process stress, the lattice mismatch between Si and SiGe/SiC assigned in different thermal-expansion coefficients such that the misfit across the interface is simulated by ANSYSTM. The simulated structures are Si/SiGe/Si and Si/SiC/Si stack mesa. The tensile strained-silicon is produced by Si/SiGe ,and the compressive one is produced by the Si/SiC. This research provides a numerical simulation of finite element method to solve stress-strain behaviors of the strained-silicon.
We propose the geometric structures and the alloy mole fraction to investigate the stress distribution in the CMOS devices by simulations. The simulated result is close to the data in the literature. This study also gives detailed analysis about the relationship between different strained-devices and strain distributions. The parametric studies can provide the design rule for the mechanical behavior of the nano-scale strained-silicon.

並列關鍵字

strain ； stress ； CMOS

參考文獻

[8] K. Oda et al., IEDM Tech Dig., pp.27-30, (2002)

[11] Kah Wee Ang, et al., “Enhanced Performance in 50 nm N-MOSFETs with Silicon-Carbon Source/Drain Regions,” IEDM, (2004)

[12] Yee-Chia Yeo, et al. “Strained Channel Transistor Using Strain Field Induced By Source and Drain Stressors, ” MRS, Vol.809 (2004)

[13] C. Gallon, et al. “Electrical analysis of external mechanical stress effects in short channel MOSFETs on (0 0 1) silicon ”, SSE, (2004)

[16] M. H. Lee, et al. “Comprehensive low-frequency and RF noise characteristics in strained-Si NMOSFETs”, IEDM Tech. Dig., pp. 69-72, (2003)