奈米級應變CMOS元件與新型非揮發性記憶體元件之研究

Study of Nanoscale Strained CMOS Devices and Novel Non-volatile Memory Devices

王維敬(Wei-Ching Wang)

指導教授 ： 張書通 ； 陳淳杰

中原大學/工學院/電子工程研究所/碩士(2006年)

https://doi.org/10.6840/cycu200600200

摘要

本論文針對局部應變矽與三維快閃記憶體兩方面來研究。在局部應變矽方面，為了能提升奈米尺寸的元件特性，由製程所引發的矽元件應變已被半導體工業所接受。這裡我們使用FLOOPS-ISE™和DESSIS-ISE™來模擬所提到的元件結構之製程與電性，其中新加坡大學於2004 IEDM發表於源極/汲極區使用矽碳(SiC)合金來增進50奈米場效N型電晶體的效能。對於NMOS而言，在源/汲極區域皆以矽碳合金(SiC)來當應力層，其電晶體通道上的應變強度與分佈視元件設計的參數而定，如：矽碳合金應力層間的距離、碳的莫耳百分比與應力層的深度都是主要的研究對象。我們可以經由理想的設計參數組合來得到一個遷移率與汲極電流均提升的理想電晶體。
在三維快閃記憶體方面，提出一個新型快閃記憶體結構來克服元件微縮上的問題，這些問題包含有在穿隧與多晶矽間介電層厚度的微縮、通道長度與電壓上的微縮。一個多重閘極的結構，可以改善元件的特性，如：次臨界擺幅與由汲極所引起的能障降低(DIBL)現象，都可以在不用考慮穿隧與多晶矽間介電層的厚度問題來達成。而垂直的結構可以克服通道的微縮問題。在此所提出的L型通道可以有效提升寫入的效率並且降低操作電壓。這裡使用DEVISE-ISE™和DESSIS-ISE™模擬其單一元件的結構與電性分析，並探討新型三維快閃記憶體與傳統快閃記憶體之間的差別。

關鍵字

矽鍺 ； 矽碳 ； 非揮發性 ； 應變

並列摘要

This paper reports the local process stress on CMOS devices and develops a new three-dimension flash memory cell. Process-induced strained silicon device technology is being adopted by the semiconductor industry to enhance the performance of the devices in the nanometer realm. Both process and device simulations for the local process stress are simulated by FLOOPS-ISE™ and DESSIS-ISE™. The simulated process is similar to the 90 nm technology with a 50 nm gate length presented by NSU (National University of Singapore) in which a tensile strain is introduced in the NMOS channel using embedded SiC pockets in the source and drain areas. The strain field in the silicon channel of a metal–oxide–semiconductor transistor with silicon–carbon alloy source and drain stressors. The magnitude and distribution of the strain components, and their dependence on device design parameters such as the spacing between the silicon-carbon alloy stressors, the carbon mole fraction in the stressors and stressor depth were investigated. We can obtain an optimum combination of the above-mentioned device design parameters in terms of mobility enhancement, drain current enhancement.
Next, a novel flash memory cell was demonstrated to overcome the scaling issues. These issues including tunneling and inter-poly dielectrics thickness scaling, channel length scaling and voltage scaling. The multi-gate structure of propose cell can improve device character such as sub-threshold slope and drain induce barrier lowering (DIBL) without scaling tunneling and inter-poly dielectrics thickness. The vertical structure can overcome channel length scaling issue. The L channel can improve the program efficiency to reducing the operating voltage. The device structure and character was simulated by device simulator DEVISE-ISE™ and DESSIS-ISE™ simulation result showing the different from conventional and novel flash memory cell.

並列關鍵字

SiC ； SiGe ； non-volatile ； strain

參考文獻

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