具閘極包圍的奈米線通道電晶體及非揮發性記憶體

Gate-All-Around Nano-wire Channel Transistors and Nonvolatile Memory Devices

陳弘斌(Hung-Bin Chen)

指導教授 ： 張俊彥 ； 吳永俊

國立交通大學/電機學院/電子工程系所/博士(2013年)

https://doi.org/10.6842/NCTU.2013.00168

摘要

本論文共分成五部份，首先此論文第一部份為多晶矽薄膜附自我熱形成矽奈米點電荷儲存層之快閃非揮發記憶體，實驗上的結果指出附奈米點電荷儲存層記憶體展現高可靠度在電荷保久度與耐久度。在一萬次的寫抹次數後，資料保久度有著可觀的好，這是由於鑲嵌在矽化氮內的矽奈米點的量子井，讓電子逃脫離開電荷儲存層不易所致，並且圓盤狀的矽奈米點有助於減緩電場的集中在奈米點之下，可使氧化層劣化的情況減小。再者，若能降低穿隧氧化層的厚度將能夠繼續降低寫抹電壓。此研究將能使用在3D堆疊高密度NAND記憶體的應用上。第二部份為研究雙高斯形狀的奈米線附有環繞式閘極在電性上的記憶體特性影響，因為介電質強度在奈米線的雙峰上不會被減低，但在谷底受應力的拉扯可能會只得氧化層的介電強度減小，因此當閘極的位置坐落在雙峰上形成雙閘極有著比較好的寫抹特性以及記憶體的考靠度。此外，附有奈米點的雙閘極記憶體的資料保久度能達到108秒僅只有17%的損失。第三部份討論二位元操作模式在環繞式閘極附有自我熱形成矽奈米點電荷儲存層之快閃非揮發記憶體，這個實驗的結果顯示二位元操作模式在通道長度為0.5µm下可藉由通道熱電子寫入和熱電洞抹除，當在通道長度為1µm下，FN穿隧機制會發生並且為主要，會使得二位元操作模式消失。環繞式閘極可降低二位元操作電壓，矽奈米點能讓二位元操作模式保有更佳的資料保久度在縱向以及側向方向。第四部份討論P型多晶矽通道閘環繞式極薄膜通道作為電晶體以及記憶體使用，使用結果顯示對於極薄的3奈米通道厚度可進行極低壓的DAHE操作，汲極小於負3伏特，閘極接地情況下，能進行量子寫入，能達到6伏特的記憶體窗口大小。因此環繞式極薄膜通道記憶體能展現低功率和高效能的特性。第五部分為討論無接面電晶體的特性，我們採用氧化薄化的方法來形成極薄膜通道將能得到非常好的電晶體特性，由於薄化可使通道多晶晶粒大小的減小以及缺陷的降低，可得到近似單晶的通道，電性上也展現出非常低的漏電流以及近乎於理想的陡峭臨界曲線，電流開關比可達到10¬¬8次方，此研究已被2013年的VLSI Technology所接受，無接面電晶體可為未來低靜態功率消耗之元件。

關鍵字

環繞式閘極 ； 奈米線 ； 薄膜電晶體 ； 多晶矽 ； 奈米點 ； 單一記憶胞二位元儲存 ； 矽-氧化矽-氮化矽-氧化矽-矽 ； 次臨界擺幅 ； 無接面電晶體

並列摘要

This thesis is divided into five parts to demonstrate 3D IC applicable nonvolatile memories and thin-film transistors with nanostructures. In the first part, a poly-Si thin-film flash NVM with a Si-nanocrystal (Si-NC) embedded charge trapping layer through self-assembly processes has been presented. Experimental results indicate that memories with the Si-NC charge trapping layer exhibits high retention and endurance characteristics. After 10k P/E cycles, the data retention is remarkable for NVM applications due to the deep quantum well of Si-NC encapsulated in the Si3N4 layer and immunity to the enhanced electric field underneath the disk-shaped Si-NCs. In addition, reducing the thickness of the tunnel oxide can further lower the P/E voltage. This investigation examines the feasibility of poly-Si thin-film nonvolatile memory with the Si-NC embedded charge trapping layer on 3-D layer-to-layer stacked high-density NAND memory applications. In the second part, the bimodal shape of bent NWs has an impact on the electrical characteristics of GAA flash memory. Since the dielectric strength is not reduced in the dual-gate cell, the dual-gate GAA poly-Si NWs flash memory has better P/E characteristics and reliability performance than the single-gate memory. Additionally, the incorporation of the Si3N4/Si-NC/Si3N4 hybrid discrete trap layer causes dual-gate devices to exhibit excellent retention (>108 seconds for 17% charge loss). In the third part, The 2-bit effect of GAA NVM with Si NCs through self-assembly processes is investigated. The experimental results reveal that the GAA Si-NCs NVM performs clear 2-bit effect with gate length of 0.5 μm by CHE programming and channel hot holes erasing. At large gate length of 1 μm, F-N tunneling occurred and dominated which resulted in the absence of the 2-bit effect. In the programming and erasing characteristics studies, the gate-all-around structure can reduce operation voltage and shorten pulse time. In the retention characteristics studies, the Si-NCs of confining electrons in the narrow region assist the gate length scaling and lateral migration. In the forth part, A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals have been successfully demonstrated. The planar and GAA structure with ultra-thin channel and a Si3N4/Si-NC/Si3N4 hybrid discrete trap layer are introduced to poly-Si TFT flash memories. The experimental results indicate that ultra-low voltage operation for 3-nm Tch device by drain avalanche hot electron injection (DAHE) condition (Vg, Vd) = (0, <-3V) can process quantum programming. The ultra-thin channel device satisfies with both ultra-low power and high performance applications, and that with Si-NCs performs large memory window and data retention. Finally, the LTPS JL-GAA TFTs with ultra-thin channel are successfully fabricated by oxidation thinning method. Our junctionless device shows quasi-crystal channel due to the reduction of grain boundaries and defects, beneficial for excellent electrical performance. This process is simple and compatible with existing CMOS processes. Such a GAA JL feature simplifies the S/D engineering and the DIBL is very small. The low IOFF and the steep SS in JL-GAA TFTs result in high on/off current ratio up to 108, which can be used in high-speed and low power consumption applications.

並列關鍵字

Gate-All-Around ； Nanowire ； Thin Film Transistor ； Polycrystalline Silicon (Poly-Si) ； Nanocrystal ； 2-bit/cell ； Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) ； Subthreshold Swing (SS) ； Junctionless Transistor

參考文獻

Chapter 1

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