一個操作在八十億赫茲具可調變相位功能之鎖相迴路

A 8GHz Phase Locked Loop With Phase Rotated Function

魏廷倫(Wei,Ting Lun)

指導教授 ： 朱大舜

國立清華大學/電機資訊學院/電機工程學系/碩士(2015年)

摘要

為應用在無線通訊領域中，本論文提出一個操作在八十億赫茲具可調變相位功能之鎖相迴路，輸入參考頻率為一億赫茲，透過鎖相迴路將其輸出頻率提高至八十億赫茲，主要應用於天線陣列當中，相較於單一天線，天線陣列可以獲得較佳的訊號雜訊比，原因是在天線陣列中，每一根天線在接收或發射訊號時，可以由電路控制產生相位差異，並且透過這些相位差異送至後端數位控制訊號處理，來提升系統之訊雜比，以及達到良好之訊號發送/接收品質。

本論文之鎖相迴路採用一階迴路濾波器(Type-I PLL)架構，其特色是無條件穩定，並且直接使用相位偵測器加上迴路濾波器組成的前饋路徑，相較於傳統的相位頻率偵測器加上電流泵的前饋路徑，前者擁有較佳的線性度，若相位偵測器的輸出不線性，雜訊將會直接饋入壓控震盪器的控制電壓，也因此相位偵測器的線性度變得十分重要。此外本論文提出一個透過兩組除二/三電路組成的相位平移電路，加上三角積分調變器，可以在維持固定的頻率下，調整鎖相迴路之輸出相位，三角積分調變器使用十二位元輸入，迴路頻寬為參考頻率之一百分之一，理由是要濾除三角積分調變器所造成的雜訊。在參考訊號源的部分，可由石英震盪器或是外部訊號產生源提供。

本論文採用台積電所提供之六十五奈米CMOS製程進行模擬設計，論文架構共分為五章，第一章介紹研究動機與背景，第二章著重於分析鎖相迴路之基本架構、子電路的操作原理與設計，第三章介紹本論文提出之操作於八十億赫茲具可調變相位功能之鎖相迴路的設計流程，包含選用架構及原理推導，接著第四章為模擬結果，最後第五章作總結，並且歸納未來的研究目標與展望。

關鍵字

鎖相迴路

並列摘要

For applications in the field of wireless communication, this thesis proposes A 8GHz Phase Locked loop with phase rotated function, the input reference frequency of 1GHz, through the phase locked loop will increase its output frequency to 8GHz, which is mainly used in antenna arrays, compared to a single antenna array antenna can get a better signal to noise ratio in, because the antenna array, each antenna when receiving or transmitting signals generated by the circuit can be controlled phase difference, and sent to the back-end digital signal processing control through these phase differences, to enhance the signal to-noise ratio, and achieve well-signal transmission / reception quality.

In this thesis, the phase locked loop circuit using a first-order filter (Type-I PLL) architecture, which features unconditionally stable, and direct use of phase detector and loop filter composed of feed forward path, compared with conventional phase frequency detector coupled with a feedforward current path of the pump, the former has a better linearity, if the phase detector output is not linear, the noise will be fed directly into a control voltage of the voltage controlled oscillator, and thus phase investigation Linearity is measured becomes very important. In addition, this paper proposes an addition to the phase shift circuit through two b / c circuit, coupled delta-sigma modulator can be maintained at a fixed frequency, output phase adjustment phase locked loop, the delta-sigma modulator using ten two yuan input, loop bandwidth of the reference frequency of one per cent, on the grounds that to filter out the noise delta-sigma modulator caused. In Part reference signal source by quartz oscillator or an external signal generation source.

In this thesis, we use 65nm CMOS process provided by TSMC,the thesis is divided into five chapters, the first chapter introduces the research motivation and background, and the second chapter focuses on the basic framework of analysis phase-locked loop, the sub-circuit The principle of operation and design proposed for the operation of the third chapter of the thesis adjustable function of varying phase locked loop design process to 8GHz equipment, including the choice of structure and principles of derivation, followed by the fourth chapter of the simulation results, and finally concluding chapter, and summarized future research goals and outlook.

並列關鍵字

Phase Locked Loop

參考文獻

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