一個八位元每秒十億次採樣頻率之數位類比轉換器

在通訊系統中，資訊主要是用數位型態作處理，但是這些資訊發射到介質中時，需要轉成類比的型態再經由載波傳送出去。因此，數位類比轉換器或類比數位轉換器是系統中不可或缺的區塊。轉換器的品質經常限制了通訊系統的速度和精準度，如能擁有高頻寬及高動態範圍的轉換器，其通訊系統就能傳送品質較優、速度就快的資訊。本論文將著重在數位類比轉換器(Digital-to-Analog Converters, DACs)上，採用的高速操作電流引導式架構，因其速度限制是來自於輸出端而非電路內部，因此此架構有利於高速下操作。然而，非理想的電流切換限制了無雜散動態範圍(spurious-free dynamic range, SFDR)的頻寬，當輸入數位信號達高頻時，無雜散動態範圍會快速地下降。為了能維持良好的高頻無雜散動態範圍，此論文在電流引導式架構中做了些許的電路改變，讓數位類比轉換器仍能在高頻下，擁有良好的無雜散動態範圍。本實驗論文中，吾人實現一個八位元、一萬兆個取樣/每秒之數位類比轉換器，使用二十八奈米之互補式金氧半場效電晶體，此數位類比轉換器在後仿真時，其無雜散動態範圍優於五十分貝，且優於四十分貝直到輸入頻率為四千六百兆赫茲，功率消耗為一百四十毫瓦。當高解析度的電流引導數位類比轉換器是必要時，電流源得高度滿足匹配特性，相對的，必須付出大面積的代價，但過大的面積會增加本質電容和雜散電容並且導致頻寬下降，改善此現象的途徑為使用較小面積的電流源。然而，小的面積電流源將引起嚴重的不匹配性，因此，需要在實際的模擬中找出同時能擁有較好的匹配性和較小的寄生電容效應的電流源。

關鍵字

八位元；每秒十億採樣頻率；靜態線性；輸入訊號瞬間暫態開關；輸入訊號負載差億

並列摘要

In communication systems, most of data stream is performed in the digital domain, but the signal carrying data stream must be transmitted by analog signals. As a result, digital-to-analog(DA) and analog-to-digital(AD) converters are necessary to be utilized. The quality of data converters usually limits the accuracy and speed of overall system. Therefore, if data converters are equiped with the characteristics of high wide band and high dynamic range, communication system will transmit data in high-end quality and high speed. This thesis focuses on the Digital-to-Analog Converters(DACs). The current-steering structure has been widely used in high-speed DACs because its can be easily achieved in high sampling speed. However, the nonideal switching limits the bandwidth of spurious-free dynamic range(SFDR). SFDR reduces rapidly while input frequency increases. Therefore, conventional current-steering structure are optimized and applied to maintain high SFDR at high sampling rate frequency. In this work, a CMOS 8-BIT 10GS/s was fabricated in a 28nm CMOS technology. In post-simulation, the DAC achieves a SFDR better than 50dB for a sinewave input frequency 1.5GHz, and better than 40 dB up to 4.5GHz. Its power consumption is roughly 140mW of power. In the design of high-accuracy current-steering DACs, current sources with high matching property are required but the penalty is large area. Larger area of current sources will enhence the value of intrinsic and parasitic capacitor loading and cause the degradation of signl bandwidth. The way to reduce capacitor loading is utilize compact current cells but compact ones have larger mismatch properties. Therefore, practical simulation is necessary to find and fit the size of current sources with high-quality matching properties and low intrinsic capacitor loading.