運用「資訊再使用距離」的多核心多層快取系統高效能初期設計最佳化方法

An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis

何芯瑀(Hsin-Yu Ho)

指導教授 ： 蔡仁松

國立清華大學/電機資訊學院/資訊工程學系所/碩士(2017年)

摘要

在本篇論文中，我們利用「資訊再使用距離」對目標程式的資料記錄做分析，並提出一個有效的方式對多核心的共享快取記憶體做最佳的設計。由於程式的資料記錄與系統硬體架構是彼此獨立的，因此設計者可以在設計初期輕易地使用我們的方式找到最佳的快取設計。我們想出一個非常有效且正確的方式對同時執行的程式產生累加的資訊再使用距離的圖形，並準確地對其效能做分析與最佳化。更重要的是，真正的共享快取記憶體的內容與累加的資訊再使用距離的圖形是相似的，因此我們提出的方法是有效的。在實驗中，利用我們的方法分析出來的快取未擊中的次數與真實的快取未擊中次數做比較，其錯誤率低於3.2％。使用一個簡單的掃描搜尋就可以在早期系統設計時決定出一個快取設計的最佳解。

關鍵字

多核心 ； 多層快取記憶體 ； 累加的資訊再使用距離

並列摘要

In this paper, we proposed an effective and efficient multi-core shared-cache design optimization approach based on reuse-distance analysis of the data traces of target applications. Since data traces are independent of system hardware architectures, a designer can easily compute the best cache design at early system design phase using our approach. We devise a very efficient and yet accurate method to derive the aggregated reuse-distance histograms of concurrent applications for accurate cache performance analysis and optimization. Essentially, the actual shared-cache contention results of concurrent applications are embedded in the aggregated reuse-distance histograms and therefore the approach is very effective. The experimental results show that the average error rate of shared-cache miss-count estimations of our approach is less than 3.2%. Using a simple scanning search method, one can easily determine the true optimal cache configurations at early system design phase.

並列關鍵字

multi-core ； multi-level-caches ； aggregated-reuse-distance

參考文獻

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