以矽鍺掩埋通道及電漿處理增進鰭式電晶體之載子遷移率與電特性研究

Enhanced Carrier Mobility and Electrical Properties in FinFETs with SiGe Buried Channel and Plasma Treatments

許奕文(Yi-Wen Hsu)

指導教授 ： 張廖貴術

國立清華大學/原子科學院/工程與系統科學系/碩士(2017年)

摘要

奈米尺寸的MOSFET，使用高介電閘層取代二氧化矽會使得載子遷移率下降，為了提升載子遷移率，通道材料的選擇及SiO2界面層的品質，扮演著重要的角色。本論文應用SiGe作為通道材料，以超晶格堆疊的方式提升載子遷移率及元件電特性。使用CF4電漿處理界面層，雖然可以降低EOT，但會有較高的介面陷阱及漏電流。因此應用O2、N2氣體電漿處理，來改善介面層的薄膜品質，提升載子遷移率。
在論文的第一部分中，使用磊晶成長Si/SiGe通道在FinFET電晶體上。SiGe材料相較於Si，具有較大的載子遷移率。比較單層SiGe通道與雙層的SiGe超晶格通道的電晶體特性，可以了解到SiGe超晶格通道結構，能在不產生應力的情況下，增加通道內Ge含量；中間插入一層應變矽以及Si-cap在通道上，能使Ge較不易擴散至界面，且能侷限載子於量子井內，因此能得到高的閘極電流、載子遷移率及較低的次臨界擺幅。以Si/SiGe super-lattice作為通道的鰭式電晶體，取得了汲極電流約為3.23x10-5A，開關電流的比例約為7個數量級，次臨界擺幅約為71 mV/dec，載子遷移率高達452 cm2/V-sec。
而在論文的第二部分中，在界面層使用CF4電漿處理能提高導通電流的情況下，結合O2或N2電漿處理，討論了對漏電流與介面缺陷修補的影響。維持CF4電漿處理的特性之下，使用O2電漿處理雖然擁有最佳的閘極電流和載子遷移率，但是漏電流大於Control元件。而使用N2電漿處理了，除了閘極電流及遷移率能獲得改善，且擁有最佳的漏電流。使用CF4+N2氣體電漿處理的鰭式電晶體元件取得了~2.7x10-5 A/cm2的閘極漏電流密度，開關電流的比例約為8個數量級，次臨界擺幅約為67.5 mV/dec，遷移率高達375 cm2/V-sec。

關鍵字

磊晶矽鍺掩埋通道 ； 電漿處理 ； 鰭式電晶體

並列摘要

The carrier mobility of MOSFET with nano-scale is reduced by replacing SiO2 with high-k gate dielectric. Channel material selection and interfacial layer quality are crucial to enhance carrier mobility. In this thesis, SiGe is used as channel material, carrier mobility and electrical properties of FinFET are enhanced by super-lattice (SL) epitaxially. Although EOT can be reduced by IL with CF4 plasma treatment, the leakage and interface trap density are increased. Hence, O2 and N2 plasma are applied to improve the interface quality.
In the first part, Si/SiGe buried channel is epitaxially grown in layer-by-layer on SOI substrate. Strained SiGe is an attractive channel material beyond Si due to its higher carrier mobility. Electrical characteristics of FinFETs with SiGe and SiGe super-lattice(SL) buried channel are investigated and compared. The diffusion of GeOx can be suppressed by Si cap in SL structure, and the mobility can be enhanced by the strained Si/SiGe structure. FinFETs with SiGe SL buried channel demonstrate higher drain current of 3.23x10-5A, On/Off ratio of 7 orders and S.S of 71 mV/dec. A very high electron mobility of 452 cm2/V-sec is achieved for FinFET with Si/SiGe SL buried channel.
Effects of O2 and N2 plasma treatment on gate leakage and defect passivation in FinFET with CF4 plasma treated interfacial layer are studied in the second part. Higher drain current and mobility in FinFETs are achieved by combining CF4 together with O2 plasma treatments, but the leakage is too large. FinFETs treated by CF4 together with N2 plasma treatments show larger drain current, higher mobility and lower leakage current. A gate leakage current of 2.7x10-5 A/cm2, on/off ratio of 8 orders, S.S of 67.5 mV/dec, mobility of 375 cm2/V-sec in Si n-FinFET are achieved by CF4+N2 plasma treatments.

並列關鍵字

SiGe buried channel ； Plasma Treatments ； FinFETs

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