改善P型高壓橫向式擴散金氧半場效電晶體大型陣列元件的自我靜電放電防護能力

Improving the ESD Self-Protection Capability of HV p-Channel LDMOS Large Array Device

陳宏維(Hung-Wei Chen)

指導教授 ： 張彌彰

國立清華大學/電機資訊學院/電子工程研究所/博士(2018年)

摘要

近年來，許多的應用諸如電源管理IC、顯示驅動IC、LED驅動IC、汽車電子和電池的應用皆需要智慧功率IC技術。這些應用中，例如高壓穩壓器，必須維持在高電壓工作，並可能利用低成本及較成熟的製程技術，如0.25微米或0.4微米的製程技術以達到較高的效益。在大多數功率IC中，金氧半場效電晶體(MOSFET)的大型陣列元件(LAD)被用於高電流驅動的輸出級。由於是在輸出級電路，大型陣列元件(LAD)還需要靜電放電(ESD)的自我防護能力。對於LAD的設計而言，必須追求低的導通電阻和較小的晶片面積開銷，難以採用靜電放電(ESD)的佈局設計規則來改善ESD性能。然而，LAD具有相當大的元件尺寸，通常期望能提供本身的靜電放電自我防護能力，而無需外掛額外的靜電放電保護元件。在本論文中，研究了如何改善0.25微米整合式雙極性/互補金氧半元件/擴散式金氧半元件 (Bipolar-CMOS-DMOS,BCD)製程製程技術中的60伏特P型高壓橫向式擴散金氧半場效電晶體大型陣列元件其自我靜電放電防護能力。我們發現原始的60伏特P型高壓橫向式擴散金氧半場效電晶體的大型陣列元件，其自我靜電放電防護能力不佳，不能透過增加元件尺寸來改善其靜電放電自我防護能力。源極工程與汲極工程被用來進行相關之研究，以便找到更有效的解決方案。發現透過在汲極端增加一道額外的P型井(PW)離子佈植，可以建立ESD自我保護能力，並對其對元件特性如安全操作區域(SOA)，特徵導通電阻(Ronsp)和崩潰電壓(BVDSS)的影響進行了更詳細的研究，並沒因為增加了ESD的防護能力而犧牲了元件的性能，並對元件佈局和優化提供了指導。關鍵的改善機制也在模擬和實驗中被驗證了。同樣的方法也被證明適用於相同BCD製程技術中的其他高壓元件。因此，本論文提出的汲極工程，是一種低成本並通用的改善方式，P型井(PW)離子佈植。可以被有效的用來改善P型高壓橫向式擴散金氧半場效電晶體大型陣列元件的自我靜電放電防護能力。

關鍵字

靜電放電 ； P型高壓橫向式擴散金氧半場效電晶體 ； 大型陣列元件 ； 自我靜電放電防護能力

並列摘要

In recent years, smart power IC technologies are needed in many applications, such as power management ICs, display driver ICs, LED driver ICs, automotive electronics and battery applications. Some of these applications, like high voltage regulators, need to sustain high supply voltage, and may take advantage of the lower cost matured technologies such as 0.25μm or 0.4μm processes. In most power ICs, large array devices (LAD) of MOSFETs are used in output stages for high current drive. Electrostatic discharge (ESD) self-protection capability of LAD is also required. For LAD design, due to the chasing of low on-resistance and smaller area overhead, it is hard to employ ESD design rules to improve ESD performance. However, with considerable device size of LAD, LAD is usually expected to provide ESD self-protection capability without adding extra ESD protection device. In this dissertation, the 60V HVPMOS LAD of the 0.25μm BCD process is studied. It was found to have poor ESD protection capability and it could not be improved by increasing the device size. Source and drain engineering approaches were developed to find a more effective solution. It was found that by adding an extra P-type well (PW) implant in the drain side, ESD self-protection capability can be established. More detailed studies on its impact to device characteristics such as SOA, Ronsp and BVDSS are carried out that provide guidelines for device layout and optimization without LAD performance losses. Key improving mechanism is verified in simulations and experiments. The same approach is also shown to be applicable to other HV devices of the BCD process. Thus, it is a low cost general solution to the HVPMOS LAD ESD protection.

並列關鍵字

ESD ； HV p-Channel LDMOS ； Large Array Device ； ESD Self-Protection Capability

參考文獻

[1] B.J. Baliga, Power Semiconductor Devices, ISBN 0-534-94098-6.

[2] Jain, Alok. Power Electronics and Its Applications. Mumbai: Penram International Publishing. ISBN 81-87972-22-X.

[3] A. Yoo, “Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs,” Thesis (PhD), University of Toronto, 2010.

[4] https://en.wikipedia.org/wiki/Power_semiconductor_device

[5] H. Wang, “Power MOSFETs with Enhanced Electrical Characteristics,” Thesis (PhD), University of Toronto, 2009.