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  • 學位論文

先進封裝錫球接點於不同溫度循環負載速率下之可靠度評估

Reliability Assessment of Advanced Packaging Solder Joints under Different Thermal Cycling Ramp Rates

指導教授 : 江國寧
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摘要


加速溫度循環測試(ATC)是被業界廣泛應用的測試條件,用以評估微電子產品封裝接點的可靠度生命週期,而常見的封裝接點破壞模式為由封裝材料熱膨脹係數(CTE)差異所產生的疲勞破壞。然而,加速溫度循環測試是項相當費時的測試項目,一次評估動則可能花上數個月的時間去完成測試,因此如何提升測試效率成為一個重要的課題。在加速溫度循環測試的參數中,溫度升降速率(ramp rate)以及持溫時間(dwell time)的調變可用以提高測試效率,但也會影響到封裝接點破壞的疲勞壽命。以溫度升降速率而言,溫度升降的快慢會對封裝接點產生不同的應力與應變,進而影響到封裝接點的材料特性與行為模式。本研究將利用材料潛變(creep)行為對封裝無鉛(lead-free)接點於不同溫度循環負載速率下進行可靠度評估。 本研究使用有限單元法搭配溫度相依的楊氏模數以及葛拉佛拉-阿瑞尼阿斯(Garofalo–Arrhenius)潛變方程式來描述封裝接點的形變行為,並採用能量密度經驗方程式搭配最佳化的網格尺寸(mesh size)。此方法可成功量化隨著不同溫度循環負載速率下所產生的封裝接點應變率效應(strain rate effect),而有限單元分析結果與實驗結果亦取得良好的一致性。本研究提供了兩個主要的貢獻,首先是建立了一個以能量密度計算的簡化壽命方程式,並於不同封裝接點幾何形狀以及封裝型態下驗證了此方程式的係數值,其封裝型態包括塑料球陣列封裝(PBGA)、覆晶封裝(flip-chip)以及晶圓級封裝(WLCSP),而其壽命預估值涵蓋數百到數千循環週期。其中,也定義了最佳網格尺寸並以不同的封裝接點幾何形狀加以驗證。其次是發展了一個新穎的無因次加速因子壽命方程式,其可以適用於描述不同溫度循環負載速率下的溫度升降速率效應以及持溫時間效應。在多變的溫度循環負載條件下,此加速因子壽命方程式預測結果展現與有限單元分析結果以及實驗結果有著高度的一致性。此外,此加速因子壽命方程式也經由文獻中數種不同的封裝型態和溫度循環負載條件加以驗證其實用性。 本研究不僅對於封裝接點於不同溫度循環負載速率下的應變率效應有深入的探討,並發展一個快速的可靠度評估方法去預測這些效應。對於封裝接點的可靠度預測可經由本研究所建立的壽命方程式達到快速有效的評估,其可以有效的減少可靠度測試時間與可能產生的研發成本。

並列摘要


Accelerated thermal cycling (ATC) test is a widely used test methodology in the semiconductor industry to assess reliability performance of packaging solder joint. A typical type of packaging solder joint failure is the propagation of fatigue cracks due to the coefficient of thermal expansion (CTE) mismatch in the interface between materials. However, ATC test is very time consuming and the test time can take more than several months. In light of it, the efficiency of ATC test has become an important topic. The parameters of ATC test, such as temperature dwell time and ramp rate, significantly influence fatigue failure in solder joints. The testing time can be reduced by fast temperature cycle, but the effects of ramp rate will cause some variations in solder joints’ material properties and mechanics behavior due to strain rate and stress changes. This study assesses solder joint reliability under different thermal cycling ramp rates based on the creep properties of lead-free material. This study uses finite element (FE) analysis with a temperature-dependent Young’s modulus and well known Garofalo–Arrhenius creep equation to assess the solder deformation behavior. An energy density-based empirical equation is used, along with the optimal mesh size for finite element simulation to determine how to accommodate the strain rate effect in solder joints caused by various thermal cycling ramp rates. A remarkable agreement in the correlation between the finite element analysis and experimental results is observed. Two major contributions emerge from this study. The first is a simplified energy density-based lifetime equation to effectively assess solder joint reliability. The equation is validated for different solder joint geometries and packaging types with lifetimes ranging from a few hundred to thousands of cycles, including plastic BGA, flip-chip, and wafer-level chip-scale packaging. In addition, an optimal mesh size is recommended for finite element simulation analysis and validated for different solder joint geometries. The second contribution is the development of a novel dimensionless acceleration-factor (AF) equation to characterize the effects of ramp rate and dwell time under varying thermal cycle loading conditions. The proposed AF equation shows high correlation with the simulation and test results for various thermal cycle loadings. In addition, the proposed AF equation is validated by confirming the consistency of its prediction results with test data on a range of packages and thermal cycling profiles reported in the literature. The research results not only reveal the strain rate effect on packaging solder joints at varying ramp rates, but also provide a quick reliability assessment methodology to accommodate this effect. The reliability of package solder joints can be analyzed using the lifetime and AF equations developed in this study, which effectively reduce reliability testing time and the fabrication costs of test runs.

參考文獻


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