低熱預算遠紅外光雷射技術應用於可三維堆疊之多晶矽電晶體

Application of Low Thermal Budget Far Infrared Ray Laser Technology on 3D Stackable Poly-Si FET

陳譽修(Chen, Yu Hsiu)

指導教授 ： 吳孟奇 ； 楊智超

國立清華大學/電機資訊學院/電子工程研究所/碩士(2016年)

摘要

本研究提出低熱預算雷射技術製作高效能可三維堆疊之多晶矽電晶體，其中包含以綠光奈秒雷射製作高品質之多晶矽通道層，以遠紅外光雷射對離子佈植後之源/汲極進行熱退火，最後在低溫下以遠紅外光雷射輔助製作金屬矽化物於源/汲極上，提升元件特性。
利用綠光奈秒雷射可將電晶體之通道層由非晶矽轉換成多晶矽薄膜，經由化學機械研磨(CMP)技術，其平均晶粒尺寸約可大於700奈米，並且可有效降低其表面粗糙度，及去除表面晶粒較小的微結晶部分。另外，利用遠紅外光雷射對源/汲極進行熱退火，將載盤溫度加熱到370oC，分別對不同摻雜的矽薄膜進行活化測試，摻雜硼和磷的片電阻可降至小於100 Ohm/sq.，摻雜砷的介於100~200 Ohm/sq.，比起快速熱退火(RTA)皆有更好的活化效果，且具有較低之熱預算。由SIMS分析發現重量較輕的硼和磷在雷射活化後，相較於RTA更不會產生擴散的現象。此外，利用兩階段升溫技術製作矽化鎳，包含第一階段的RTA(250oC, 30秒)，以及低溫情況的第二階段遠紅外光雷射，由此在表面形成NiSi薄層以降低接觸阻抗。此矽化物除了跟兩階段RTA製作之矽化物可達到相同的阻抗，也具有更低之熱預算。
我們將上述的實驗技術整合至多晶矽電晶體，得到驅動電流最高可達到285A/m (n型元件)及111A/m (p型元件)，同時將在論文中討論不同元件尺寸對電性造成的影響。由上述雷射技術製作之多晶矽電晶體除了有較好的電特性，也因為具有較低熱預算，因此有利於發展三維堆疊元件。

關鍵字

低熱預算技術 ； 綠光奈秒雷射結晶 ； 遠紅外光雷射退火 ； 雷射輔助製作自我對準矽化物 ； 可三維堆疊電晶體

並列摘要

In this thesis, we propose low thermal budget laser technologies to fabricate high-performance 3D stackable poly-Si FET, including green nanosecond laser used to produce high-quality poly-Si channel, far infrared ray laser used to anneal source / drain regions after ion implantation and form the metal silicide layer on the source / drain, thereby improves the device performance.
Green nanosecond laser is employed to transform the channel layer of the device from a-Si to poly-Si thin film. After chemical mechanical polishing (CMP) process, the average grain size is larger than 700nm, and the mean surface roughness can be lowered efficiently; moreover, the nc-Si on the surface can be polished. Far infrared ray (FIR) laser is utilized to anneal the source / drain regions. Silicon films with various doping species are activated by FIR laser after the substrate temperature is raised to 400oC, and the sheet resistances of sub-100Ω/□ for both B/P-doped Si and 100~200Ω/□ for As-doped Si can be realized. It significantly outperforms rapid thermal anneal (RTA) process and obsesses lower thermal budget. In addition, the dopant profiles of boron and phosphorus observed by SIMS analysis are less diffused than the data prepared by RTA process. Finally, we produce NiSi layer by two-step annealing processes, involving RTA (250oC, 30s) for the first step and FIR laser at low temperature for the second step. After that, NiSi layer which has low resistivity is formed on the surface and is used to lower the contact resistance. Silicide made from these ways has lower thermal budget and it can obtain equivalent resistance in comparison with two-step RTA processes.
We integrate the technologies mentioned above to the poly-Si FET, and the highest drive current can be reached to 285A/m for n-type and 111A/m for p-type respectively. The effect of different device sizes on the electrical characteristics will also be discussed in this thesis. The poly-Si FET fabricated from these methods not only has better electrical properties but also has lower thermal budget, thus it is beneficial to develop 3D sequential layered devices.

並列關鍵字

low thermal budget technology ； green nanosecond laser crystallization ； far infrared ray laser anneal ； laser-assisted salicide ； 3D stackable FETs

參考文獻

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